Patents by Inventor Niranjan Mylarappa Gowda

Niranjan Mylarappa Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220224899
    Abstract: Examples relate to an encoding apparatus, encoding device, encoding method, computer program and to a corresponding computer system. An encoding apparatus comprises processing circuitry configured to encode at least two video streams to perform video compression encoding using one or more encoders, wherein the one or more encoders are each configured to deter-mine an encoding context based on the video stream processed by the respective encoder, the encoding context comprising at least one or more reference frames determined by the respective encoder. The processing circuitry is configured to store at least one of the encoding contexts determined by the one or more encoders in a shared memory portion of the memory circuitry that is accessible to the one or more encoders. The processing circuitry is configured to proceed, using the one or more encoders, with encoding the at least two video streams based on an encoding context stored in the shared memory portion.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Andrey BELOGOLOVY, Evgeny STUPACHENKO, Niranjan MYLARAPPA GOWDA
  • Publication number: 20220138548
    Abstract: An analog neural network including a hardware activation function is provided. A layer of the analog neural network includes a sequence of processing elements that receives analog signals, perform MAC operations on the analog signals, and generates analog outputs. The analog outputs are provided to an analog circuitry that can apply an activation function on the analog outputs. The output of the analog circuitry are also analog signals, which can further be provided to the next layer in the network. The analog circuitry may include a differential pair of transistors to compute the tan h activation function. Alternatively, the analog circuitry may include a comparator and multiplexer to compute the ReLU activation function. Compared with digital implementation of activation functions, the analog circuitry eliminates the need of converting the analog outputs of the layer to digital signals and the need of converting the result of the activation function to analog signals.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: Hechen Wang, Niranjan Mylarappa Gowda, Andrey Belogolovy
  • Patent number: 9825737
    Abstract: The detection and validation of Secondary Synchronization Signal comprising generating a set of samples by performing DFT operation on a time domain LTE signal, wherein the signal comprising an LTE frame divided into an even half and odd half frame, First and second set of hypotheses from even samples in even and odd half frame are generated and third and fourth set of hypotheses from odd samples in even and odd half frame are generated using first and second hypotheses. Even half frame is selected as start of boundary of the frame when location of the peak of first hypotheses is smaller than that of second hypotheses or location of the peak of fourth hypotheses is smaller than that of third hypotheses. The physical layer cell identity is determined from the locations of the peak of the first, second, third and fourth set of hypotheses averaged over multiple frames.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 21, 2017
    Assignee: Lekha Wireless Solutions Pvt Ltd.
    Inventors: Niranjan Mylarappa Gowda, Sreenath Ramanath
  • Patent number: 9621340
    Abstract: The input samples transmitted by the base station are decimated and the decimated samples are correlated with the three reference PSS sequences to obtain the correlation results. The correlation results are differentially combined to obtain the hypotheses. The hypotheses are grouped into windows. The peaks across windows of multiple half frames are selected and obtained peaks are averaged over the multiple half frames to detect the half frame boundary window. Reference PSS versions are generated for ICFO estimation. The hypotheses are generated in the HFBW. The highest averaged hypothesis is selected to estimate ICFO. The ICFO error is corrected by adjusting a reference clock signal. The decimated samples are correlated and differentially combined around the HFB to determine a HFB and a FCFO from the peak value of the hypotheses. The received samples are correlated and differentially combined around the half frame boundary to further refine HFB and FCFO estimations.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 11, 2017
    Assignee: Lekha Wireless Solutions Pvt Ltd.
    Inventors: Niranjan Mylarappa Gowda, Sreenath Ramanath
  • Publication number: 20160165613
    Abstract: The detection and validation of Secondary Synchronization Signal comprising generating a set of samples by performing DFT operation on a time domain LTE signal, wherein the signal comprising an LTE frame divided into an even half and odd half frame, First and second set of hypotheses from even samples in even and odd half frame are generated and third and fourth set of hypotheses from odd samples in even and odd half frame are generated using first and second hypotheses. Even half frame is selected as start of boundary of the frame when location of the peak of first hypotheses is smaller than that of second hypotheses or location of the peak of fourth hypotheses is smaller than that of third hypotheses. The physical layer cell identity is determined from the locations of the peak of the first, second, third and fourth set of hypotheses averaged over multiple frames.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Inventors: Niranjan Mylarappa Gowda, Sreenath Ramanath
  • Patent number: 9031124
    Abstract: A method of generating a hypothesis and estimating a CFO includes receiving a signal including a set of radio frames, dividing each received radio frame of the set into a set of received sub-sequences, dividing, each of reference radio frames from a reference signal stored in the receiver into a set of reference sub-sequences, correlating the set of received sub-sequences with the set of reference sub-sequences to obtain a set of correlation values, generating, a first value set and a second value set of hypothesis based on the correlation values, generating a first and a second hypothesis based on the first value and the second value set, and averaging the first and the second hypothesis to obtain an averaged hypothesis, performing a DFT on the averaged hypothesis to obtain a DFT sequence, determining a peak position of the DFT sequence, and estimating the CFO based on the peak position.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: May 12, 2015
    Inventors: Shrinivas Bhat, Niranjan Mylarappa Gowda