Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

Abstract: An integrated passive device transmission-line resonator is disclosed herein. An example structure of the transmission-line resonator includes a glass substrate having first and second sides, a ground plane, a dielectric layer, and features fabricated from two metal layers. A first metal layer, which is formed on the second side of the glass substrate, includes a first capacitor plate and a conductor that, in conjunction with a portion of the ground plane, realizes a transmission line. A portion of the dielectric layer is disposed between the first capacitor plate and a second capacitor plate, which is formed from a second metal layer and positioned axially above the first capacitor plate, to form a capacitor. A smooth interface between a surface of the second side of the glass substrate and the conductor reduces transmission losses of signals propagating across the transmission line and increases performance of the transmission-line resonator.

Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.

Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

Abstract: An inductor-capacitor (LC) filter includes an inductor having an asymmetric shape including at least one turn. The LC filter also includes serial capacitors coupled to the inductor at only one end of a continuous portion of the inductor. The serial capacitors continues the shape of the inductor. The capacitors are outside of a footprint of the continuous portion of the inductor.

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

Abstract: To overcome the deficiencies of conventional rectangular circuit wafers, a glass substrate circuit wafer with an obtuse angle on the perimeter may be used. In one example, a glass substrate wafer may include a first circuit on a first portion of a glass substrate and a second circuit on a second portion of the glass substrate where the first portion has a first obtuse angle and the second portion has a second obtuse angle that is complementary to the first obtuse angle on the perimeter of the first portion to mate together to form an outer perimeter that comprises right angles.