Patents by Inventor Niranjan Talwalkar
Niranjan Talwalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9813085Abstract: A system and method for calibrating digital pre-distortion in a wireless device. A pre-distortion circuit may output a first training signal while a power amplifier of the wireless device is on, to generate a first feedback signal. The first feedback signal may be fed back to the pre-distortion circuit via a receive path of the wireless device. The pre-distortion circuit may output a second training signal while the power amplifier is off, to generate a second feedback signal. The second feedback signal may be fed back to the pre-distortion circuit via the receive path. The pre-distortion circuit may then determine one or more pre-distortion coefficients based on the first and second feedback signals.Type: GrantFiled: September 23, 2016Date of Patent: November 7, 2017Assignee: QUALCOMM IncorporatedInventors: Paul Brandon Butler, James Gardner, Niranjan Talwalkar, Burcin Baytekin
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Patent number: 9712115Abstract: A current-mode power amplifier is disclosed. In some embodiments, the power amplifier may include a first cascode transistor pair including a first transfer function coupled to a second cascode transistor pair including a second transfer function. The first transfer function may be an inverse of the second transfer function. The current-mode power amplifier may also include an inductive-capacitive (LC) resonant circuit to reduce the effects of gate capacitances of the first cascode transistor pair and the second cascode transistor pair. In some embodiments, the current-mode power amplifier may include a bias current controller. The bias current controller may adjust transistor bias currents based, at least in part, on an input signal received by the current-mode power amplifier.Type: GrantFiled: November 24, 2015Date of Patent: July 18, 2017Assignee: QUALCOMM IncorporatedInventor: Niranjan Talwalkar
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Publication number: 20170149389Abstract: A current-mode power amplifier is disclosed. In some embodiments, the power amplifier may include a first cascode transistor pair including a first transfer function coupled to a second cascode transistor pair including a second transfer function. The first transfer function may be an inverse of the second transfer function. The current-mode power amplifier may also include an inductive-capacitive (LC) resonant circuit to reduce the effects of gate capacitances of the first cascode transistor pair and the second cascode transistor pair. In some embodiments, the current-mode power amplifier may include a bias current controller. The bias current controller may adjust transistor bias currents based, at least in part, on an input signal received by the current-mode power amplifier.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Inventor: Niranjan Talwalkar
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Patent number: 9076366Abstract: In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator.Type: GrantFiled: February 16, 2012Date of Patent: July 7, 2015Assignee: Aquantia Corp.Inventors: Niranjan Talwalkar, Moshe Malkin
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Publication number: 20130214829Abstract: In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: PLX Technology, Inc.Inventors: Niranjan TALWALKAR, Moshe MALKIN
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Patent number: 7602256Abstract: Systems, circuits, and techniques for the calibration and fast tuning of VCOs in PLLs are provided. Information for coarse tuning before normal operation are calculated and stored. These systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques involve: determining a digital code Dc, to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, these systems and techniques involve: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.Type: GrantFiled: May 8, 2008Date of Patent: October 13, 2009Assignee: NanoAmp Solutions, Inc. (Cayman)Inventor: Niranjan Talwalkar
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Publication number: 20090088110Abstract: A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.Type: ApplicationFiled: September 24, 2008Publication date: April 2, 2009Applicant: NANOAMP SOLUTIONS, INC. (CAYMAN)Inventors: Axel Schuur, Nianwei Xing, David H. Shen, Chien-Meen Hwang, Ann P. Shen, Niranjan Talwalkar
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Publication number: 20080204151Abstract: The present invention provides novel systems and techniques for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques include the steps of: determining a digital code Dc, to coarse tune to a calibration frequency, FC; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.Type: ApplicationFiled: May 8, 2008Publication date: August 28, 2008Applicant: NANOAMP SOLUTIONS, INC.Inventor: Niranjan Talwalkar
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Patent number: 7382199Abstract: The present invention provides novel methods for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these methods decrease significantly the time needed for a PLL to transition from one frequency to another. These methods include the steps of: determining a digital code Dc to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency, F.Type: GrantFiled: February 3, 2006Date of Patent: June 3, 2008Assignee: NanoAmp Solutions, Inc.Inventor: Niranjan Talwalkar
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Publication number: 20070182494Abstract: The present invention provides novel methods for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these methods decrease significantly the time needed for a PLL to transition from one frequency to another. These methods include the steps of: determining a digital code Dc to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency, F.Type: ApplicationFiled: February 3, 2006Publication date: August 9, 2007Inventor: Niranjan Talwalkar
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Patent number: 7236044Abstract: Method and apparatus for adjusting an impedance of a substrate of a Metal-Oxide-Semiconductor (MOS) transistor by providing a bias voltage and connecting a frequency-selective circuit between the substrate and the bias voltage. The frequency-selective circuit is also provided with at least one reactive element, such as an inductive element or a capacitive element, to obtain a certain frequency-response of the frequency-selective circuit and thus adjusts the substrate impedance of the MOS transistor. The method and apparatus are compatible with standard CMOS technology and applicable to RF switches, including T/R switches for processing high-frequency analog signals.Type: GrantFiled: October 13, 2004Date of Patent: June 26, 2007Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Niranjan Talwalkar, Chik P. Yue, S. Simon Wong
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Patent number: 7015768Abstract: A low-phase-noise and high-performance voltage-controlled oscillator (VCO) uses a noise-canceling differential varactor topology. An implementation includes circuitry for a fully-differential varactor-inductor oscillator for reduced noise and improved performance. Susceptibility to common-mode noise sources coupled into the varactors is reduced.Type: GrantFiled: August 27, 2004Date of Patent: March 21, 2006Assignee: IRF Semiconductor, Inc.Inventor: Niranjan Talwalkar
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Publication number: 20050110558Abstract: Method and apparatus for adjusting an impedance of a substrate of a Metal-Oxide-Semiconductor (MOS) transistor by providing a bias voltage and connecting a frequency-selective circuit between the substrate and the bias voltage. The frequency-selective circuit is also provided with at least one reactive element, such as an inductive element or a capacitive element, to obtain a certain frequency-response of the frequency-selective circuit and thus adjusts the substrate impedance of the MOS transistor. The method and apparatus are compatible with standard CMOS technology and applicable to RF switches, including T/R switches for processing high-frequency analog signals.Type: ApplicationFiled: October 13, 2004Publication date: May 26, 2005Inventors: Niranjan Talwalkar, Chik Yue, S. Wong