Abstract: Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Multiple methods of manufacturing such memory devices are described to provide improved protection of replacement gate structures, such as word lines and word line liners. These include multiple processing flows which forming one or more additional barrier structures between structures subject to at least partial removal during the processing flow; wherein some portion of the additional barrier structure(s) will remain at the end of manufacturing.

Abstract: Methods, systems, and devices for methods for selectively depositing carbon on substrates by atomic layer deposition are described. The described techniques include single precursor and multiple precursor atomic layer deposition processes. For instance, a device may react a first precursor with a first material and a second material to form a carbon compound on the first material and not the second material. The materials may be associated with different growth delays based on being exposed to the first precursor. Multiple precursors may be used where one or both of the precursors may have different growth delays for the first and second materials.

Abstract: Methods, systems, and devices for memory cell formation in pier and pillar architectures are described. A stack of materials including alternating layers of nitride and oxide may be formed, and a plurality of columns of a third material may be formed in the stack. The third material may be recessed (e.g., laterally) filled with at least an electrode liner and a metal material. Portions of the nitride material and an oxide liner that are adjacent to the third material may be removed, and a second electrode liner may be formed (e.g., in the regions from which the nitride material and oxide liner were removed). Memory cells may be formed after removing the portion of the nitride material and oxide liner such that the cells are in contact with the second electrode liner.

Abstract: Distributor assemblies for vapor transport deposition systems, and methods of conducting vapor transport deposition, are described.

Abstract: Distributor assemblies for vapor transport deposition systems, and methods of conducting vapor transport deposition, are described.

Abstract: Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.

Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.

Abstract: Distributor assemblies for vapor transport deposition systems, and methods of conducting vapor transport deposition, are described.

Abstract: Distributor assemblies for vapor transport deposition systems, and methods of conducting vapor transport deposition, are described.

Abstract: Distributor assemblies for vapor transport deposition systems, and methods of conducting vapor transport deposition, are described.

Abstract: Systems and methods for forming solar cells with CuInSe2 and Cu(In,Ga)Se2 films are provided. In one embodiment, a method comprises: during a first stage (220), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 223) and Se vapor (121, 225) to deposit a semiconductor film (212, 232, 252) upon a substrate (114, 210, 230, 250); heating the substrate (114, 210, 230, 250) and the semiconductor film to a desired temperature (112); during a second stage (240) following the first stage (220), performing a mass transport through vapor transport of a copper chloride (CuClx) vapor (143, 243) and Se vapor (121, 245) to the semiconductor film (212, 232, 252); and during a third stage (260) following the second stage (240), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 263) and Se vapor (121, 265) to the semiconductor film (212, 232, 252).

Abstract: Systems and methods for forming solar cells with CuInSe2 and Cu(In,Ga)Se2 films are provided. In one embodiment, a method comprises: during a first stage (220), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 223) and Se vapor (121, 225) to deposit a semiconductor film (212, 232, 252) upon a substrate (114, 210, 230, 250); heating the substrate (114, 210, 230, 250) and the semiconductor film to a desired temperature (112); during a second stage (240) following the first stage (220), performing a mass transport through vapor transport of a copper chloride (CuClx) vapor (143, 243) and Se vapor (121, 245) to the semiconductor film (212, 232, 252); and during a third stage (260) following the second stage (240), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 263) and Se vapor (121, 265) to the semiconductor film (212, 232, 252).