Abstract: A semiconductor package having one or more bifacial NAND memory devices includes an interposer including a plurality of multiplexers (MUX) integrally formed within the interposer, and a plurality of bifacial NAND memory devices disposed over the interposer. The bifacial NAND memory devices are electrically coupled to the MUX. Each bifacial NAND memory device includes a first NAND memory die disposed on a first planar surface, and a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, and adjacent the interposer. Each bifacial NAND memory device also includes a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die with the second NAND memory die, and the MUX.