Patents by Inventor Nirmal Nepal

Nirmal Nepal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240296122
    Abstract: Systems and methods for caching metadata. In some embodiments, in response to an access request comprising an application memory address, it may be determined whether the application memory address matches an entry of at least one cache. In response to determining that the application memory address does not match any entry of the at least one cache: the application memory address may be used to retrieve application data; the application memory address may be mapped to at least one metadata memory address; and the at least one metadata memory address may be used to retrieve metadata corresponding to the application memory address. An entry in the at least one cache may be created, wherein: the entry is indexed by the application memory address; and the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 5, 2024
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Nirmal Nepal
  • Publication number: 20210055954
    Abstract: Systems and methods for a write interlock configured to perform first processing and second processing, decoupled from the first processing. In some aspects, the first processing comprises receiving, from a processor, a store instruction including a target address, storing, in a data structure, a first entry corresponding to the store instruction, initiating a check of the store instruction against at least one policy, and in response to successful completion of the check, removing the first entry from the data structure. The second processing comprises receiving, from the processor, a write transaction including a target address, determining whether any entry in the data structure relates to the target address of the write transaction, and in response to determining that no entry in the data structure relates to the target address of the write transaction, causing the data to be written to the target address of the write transaction.
    Type: Application
    Filed: February 1, 2019
    Publication date: February 25, 2021
    Applicant: Dover Microsystems, Inc.
    Inventors: Steven Milburn, Nirmal Nepal