Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.

Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.

Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Abstract: A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all other cell match lines. The reference dummy match line triggers a dummy sensing block to initiate a time window for sensing the dummy match line. By this time, all other array match lines will have been stabilized and have reached their respective sensing blocks, to then allow the data to be latched. The match sensing circuit provided may be applied to a variety of arrangements including BCAMs and TCAMs.

Abstract: A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM device of the serial cascade arrangement receives a portion of the search word. Each of the CAM devices in the serial cascade arrangement includes a CAM, a plurality of GMAT lines, a dummy match line, and a GMAT interface circuitry. The GMAT interface circuitry facilitates driving the match signals from a substantially previous CAM to a substantially adjacent CAM. The last CAM device is coupled to a match latch and a priority encoder.

Abstract: A tracking circuit in a memory unit which generates sense enable signals at optimal time instances. The tracking circuit includes a scalable driver block containing a number of dummy cells, each having a drive strength identical to the drive strength of a cell in a memory array. The dummy cells are turned on and drive a column as would the memory cells in the memory array. As a result, the scalable driver block approximates the delay caused by (a number of rows in) a column at least when the number of rows is large. An inverse control logic emulates the delay in case of a smaller number of rows, and one of the inverse control logic and the scalable driver blocks provides a pulse, which is used to trigger a sense operation.