Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: Example techniques are described for image processing to selectively perform a warping operation if there is change in orientation of a display device between frames. For example, if there is change in orientation of a display device between processing a first frame and after rendering of a second frame, processing circuitry may perform a warp operation on the second frame to warp image content of the second frame based on a current orientation of the display device. If there is no change in orientation of the display device between processing a third frame and after rendering of a fourth frame, the processing circuitry may bypass the warp operation on the fourth frame to avoid warping entire image content of the fourth frame.

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: Frame buffering technologies are described. An example device includes camera hardware configured to receive a plurality of frames, a first memory device that implements a buffer, and a second memory device that consumes greater power than the first memory device. The device also includes processing circuitry coupled to the camera hardware, and to the first and second memory devices. The processing circuitry is configured to form a plurality of snapshot frames using a subset of the plurality of the received frames, to store the plurality of snapshot frames to the buffer implemented in the first memory device, and to receive a capture command. In response to receiving the capture command, the processing circuitry may identify, as a capture-selected snapshot frame, a first snapshot frame of the plurality of snapshot frames stored to the buffer, and push the capture-selected snapshot frame to the second memory device.

Abstract: Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.

Abstract: The present disclosure provides for systems, methods, and apparatus for image processing. These systems, methods, and apparatus may compare a current frame to at least one previous frame to determine an amount of difference. The amount of difference between the current frame and the at least one previous frame may be compared to a threshold value. Additionally, the frame rate may be adjusted based on the comparison of the amount of difference between the current frame and the at least one previous frame and the threshold value. Another example may determine an amount of perceivable difference between a current frame and at least one previous frame and adjust a frame rate based on the determined amount of perceivable difference between the current frame and the at least one previous frame.

Abstract: Methods and apparatus for controlling at least two processing cores in a multi-processor device or system include accessing an operating system run queue to generate virtual pulse trains for each core and correlating the virtual pulse trains to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processing cores to provide a performance level that accommodates interdependent processes, threads and processing cores.

Abstract: Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.