Patents by Inventor Nishant Madan

Nishant Madan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof
    Patent number: 9599672
    Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Anurag Jindal, Nishant Madan, Mayank Tutwani
  • INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF
    Publication number: 20160169966
    Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: KUMAR ABSHISHEK, Anurag Jindal, Nishant Madan, Mayank Tutwani