Patents by Inventor Nishant Patel

Nishant Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220046649
    Abstract: A user equipment (UE) may perform multiple searches within a specified search period to locate the wireless band that provides the most throughput. For instance, if the UE finds a low band with time remaining in the search period, the UE continues to search for a higher frequency wireless. In some examples, the UE attempts to locate a high band within a next portion of the search period. If the UE finds the high band, then the UE will use that band since it provides the most throughput of the available bands. If the UE does not find the high band, then the UE searches for a mid-band for another portion of the search time. By prioritizing higher bands over the first available band that is located in the initial search, the UE will connect to the band that provides the best user experience and the most throughput.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventors: Wafik Abdel Shahid, Ming Shan Kwok, Nishant Patel
  • Patent number: 11222154
    Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Rajarshi Mukherjee, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav Pratap, Nishant Patel, Malitha Kulatunga, Sachin Bansal
  • Publication number: 20210110093
    Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 15, 2021
    Inventors: Kaushik DE, Rajarshi MUKHERJEE, David L. ALLEN, Bhaskar PAL, Sanjay GULATI, Gaurav PRATAP, Nishant PATEL, Malitha KULATUNGA, Sachin BANSAL
  • Publication number: 20190205736
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Amit Bleiweiss, Abhishek Venkatesh, Gokce Keskin, John Gierach, Oguz Elibol, Tomer Bar-On, Huma Abidi, Devan Burke, Jaikrishnan Menon, Eriko Nurvitadhi, Pruthvi Gowda Thorehosur Appajigowda, Travis T. Schluessler, Dhawal Srivastava, Nishant Patel, Anil Thomas
  • Publication number: 20070260066
    Abstract: The present invention relates to the process for the preparation of compounds of formula (I) or its pharmaceutically acceptable salts Formula I The novel compounds (i) 10,11-Anhydro-2?,4?-di-O-benzoyl-12-O-imidazolylcarbonyl-6-O-methylerythromycin A of formula (Xa) Formula (Xa) (ii) 2?,4?-di-O-benzoyl-11-amino-11-N-[4-[4-(3-pyridyl)imidazol-1-yl]butyl]-11-deoxy-6-O-methylerythromycin A 11,12-cyclic carbamate of formula (XIa) Formula (XIa) (iii) 2?-O-benzoyl-11-amino-11-N-[4-[4-(3-pyridyl)imidazol-1-yl]butyl]-11-deoxy-5-O-desosaminyl-6-O-methylerythronolide A 11,12-cyclic carbamate of formula (XIIa) Formula (XIIa) (iv) 2?-benzoyl-11-amino-11-N-[4-[4-(3-pyridyl)imidazol-1-yl]butyl]-11-deoxy-5-O-desosaminyl-6-O-methylerythronolide A 11,12-cyclic carbamate of formula (XIIa) Formula (XIIa) and their use as intermediates in formation of compound of Formula I. Also the process of preparation of compound of formula (XIIIa).
    Type: Application
    Filed: April 25, 2005
    Publication date: November 8, 2007
    Applicant: Alembic Limited
    Inventors: Suhas Sohani, Mandar Deodhar, Nishant Patel, Manish Patel, Mahesh Davadra, Vinodhamar Kansal