Patents by Inventor Nishant Patil

Nishant Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200341931
    Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Inventors: Pankaj Makhija, Nishant Patil
  • Publication number: 20200285524
    Abstract: Methods, systems, and apparatus, including an apparatus for generating clusters of building blocks of compute nodes using an optical network. In one aspect, a method includes receiving request data specifying requested compute nodes for a computing workload. The request data specifies a target n-dimensional arrangement of the compute nodes. A selection is made, from a superpod that includes a set of building blocks that each include an m-dimensional arrangement of compute nodes, a subset of the building blocks that, when combined, match the target n-dimensional arrangement specified by the request data. The set of building blocks are connected to an optical network that includes one or more optical circuit switches. A workload cluster of compute nodes that includes the subset of the building blocks is generated. The generating includes configuring, for each dimension of the workload cluster, respective routing data for the one or more optical circuit switches.
    Type: Application
    Filed: April 11, 2019
    Publication date: September 10, 2020
    Inventors: Nishant Patil, Xiang Zhou, Andrew Swing
  • Publication number: 20200117999
    Abstract: Methods, systems, and apparatus for updating machine learning models to improve locality are described. In one aspect, a method includes receiving data of a machine learning model. The data represents operations of the machine learning model and data dependencies between the operations. Data specifying characteristics of a memory hierarchy for a machine learning processor on which the machine learning model is going to be deployed is received. The memory hierarchy includes multiple memories at multiple memory levels for storing machine learning data used by the machine learning processor when performing machine learning computations using the machine learning model. An updated machine learning model is generated by modifying the operations and control dependencies of the machine learning model to account for the characteristics of the memory hierarchy. Machine learning computations are performed using the updated machine learning model.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Doe Hyun Yoon, Nishant Patil, Norman Paul Jouppi
  • Publication number: 20190155658
    Abstract: Methods, systems, and computer storage media storing instructions for managing processing system efficiency. One of the methods includes obtaining data splitting a plurality of general-purpose processing units in a processing system into a high-priority domain and a low-priority domain, wherein the general-purpose processing units in the high-priority domain are assigned to perform one or more tasks comprising one or more high-priority tasks, and the general-purpose processing units in the low-priority domain are assigned to perform one or more low-priority tasks; and during runtime of the processing system, obtaining memory usage measurements that characterize usage of system memory by the high-priority domain and the low-priority domain; and adjusting, based on the memory usage measurements, a configuration of (i) the high-priority domain, (ii) the low-priority domain, or (iii) both to adjust utilization of the system memory by the general-purpose processing units.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 23, 2019
    Inventors: Liqun Cheng, Rama Krishna Govindaraju, Haishan Zhu, David Lo, Parthasarathy Ranganathan, Nishant Patil
  • Patent number: 10073817
    Abstract: The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are organized into specially ordered vectors, which are multiplied together to produce a portion of a product matrix.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: September 11, 2018
    Assignee: Google LLC
    Inventors: Nishant Patil, Matthew Sarett, Rama Krishna Govindaraju, Benoit Steiner, Vincent O. Vanhoucke
  • Patent number: 9830303
    Abstract: The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are organized into specially ordered vectors, which are multiplied together to produce a portion of a product matrix.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: November 28, 2017
    Assignee: Google Inc.
    Inventors: Nishant Patil, Matthew Sarett, Rama Krishna Govindaraju, Benoit Steiner, Vincent O. Vanhoucke
  • Patent number: 9645974
    Abstract: The present disclosure relates to optimized matrix multiplication using vector multiplication of interleaved matrix values. Two matrices to be multiplied are organized into specially ordered vectors, which are multiplied together to produce a portion of a product matrix.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 9, 2017
    Assignee: Google Inc.
    Inventors: Nishant Patil, Matthew Sarett, Rama Krishna Govindaraju, Benoit Steiner, Vincent O. Vanhoucke
  • Patent number: 9218294
    Abstract: An access instruction which includes a logical block address (LBA) is received. A first-level table is accessed to obtain a first-level table entry associated with the LBA. From the first-level table entry, a location associated with a second-level table on solid state storage media is determined. The second-level table is accessed at the determined location to obtain a second-level table entry associated with the LBA. From the second-level table entry, a physical block address corresponding to the logical block address is determined.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 22, 2015
    Assignee: SK Hynix memory solutions inc.
    Inventors: Nishant Patil, Derrick Preston Chu, Nandan Sridhar, Prasanthi Relangi
  • Patent number: 8832539
    Abstract: Old user data, old metadata, and old error correction parity information are received. New metadata corresponding to the old user data is generated. The old metadata and the new metadata are combined to obtain combined metadata. New error correction parity information is generated using the combined metadata. The old error correction parity information and new error correction parity information are combined to obtain combined error correction parity information. The old user data, new metadata, and combined error correction parity information are stored in solid state storage.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 9, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Nishant Patil, Meng-Kun Lee, Yingquan Wu
  • Patent number: 8065634
    Abstract: A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: November 22, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Nishant Patil, Subhasish Mitra
  • Patent number: 7911234
    Abstract: A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: March 22, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Nishant Patil, Subhasish Mitra