Abstract: A reference voltage generator includes first through sixth transistors and an operational amplifier. The first and second transistors provide first and second voltages to the operational amplifier, respectively. The operational amplifier generates a control voltage at its output terminal, which then is provided to the gate terminals of the second and third transistors. The output terminal of the operational amplifier also is connected to the fifth and sixth transistors by way of trimming switches. The trimming switches provide fine trimming control of a reference output voltage.

Abstract: A power management controller (PMC) for resetting various voltage domains of an integrated circuit (IC) generates and transmits first and second voltage domain input signals to first and second voltage domains, respectively, and generates corresponding reset signals for resetting the first and second voltage domains. The PMC generates a first master reset signal indicative of resetting the first and second voltage domains when the first and second voltage domains are booting. The PMC generates a second master reset signal indicative of resetting the first and second voltage domains when the IC is in a functional mode. The PMC determines whether the first and second voltage domains are non-functional and if at least one is non-functional, then the PMC masks a respective one of the first and second reset signals.

Abstract: An integrated circuit (IC) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. A resistor-ladder network receives the feedback signal and generates a sense voltage signal. A voltage regulator compares the sense voltage signal with a reference voltage signal and regulates the first supply voltage signal at a first voltage level.

Abstract: A reference voltage generator that does not require a start-up circuit or a feedback loop generates a proportional-to-absolute-temperature (PTAT) output voltage based on two complementary-to-absolute-temperature (CTAT) currents. The reference voltage generator provides a reference voltage that is a sum of the PTAT output voltage and a CTAT voltage.

Abstract: A voltage switching system for an integrated circuit (IC) operable in first and second operational modes includes a handover module, first and second voltage regulators, a switch driver, a transistor, and a comparator. When the IC transitions between modes, the handover module receives ramp control and hand-over start signals, generates comparator and bandwidth control signals based on the hand-over start signal and a ramp signal based on the ramp control signal. The switch driver generates a power control signal based on the comparator control signal and a gate input signal based on the ramp signal. The comparator compares first and second voltage signals based on the power control signal and generates a hand-over complete signal. The handover module generates a final hand-over complete signal based on the hand-over complete signal, indicative of completion of transition between the first and second operational modes.

Abstract: An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.

Abstract: An integrated circuit (IC) includes a power grid having first, through fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively, a voltage regulator, a reference voltage calibration circuit, a dual-rail sense circuit, and a voltage monitor circuit. The reference voltage calibration circuit receives the first supply, first ground, second supply, and second ground voltage signals and generates a reference voltage signal based on differences between voltage levels of the first supply and ground voltage signals, and the second supply and ground voltage signals. The voltage regulator regulates the first supply voltage signal based on the reference voltage signal and the second supply voltage signal. The dual-rail sense circuit generates a sense signal based on the second supply and ground voltage signals. The voltage monitor generates a voltage monitor signal based on the sense signal that indicates a state of the IC.

Abstract: An integrated circuit (IC) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. A resistor-ladder network receives the feedback signal and generates a sense voltage signal. A voltage regulator compares the sense voltage signal with a reference voltage signal and regulates the first supply voltage signal at a first voltage level.

Abstract: A voltage converter such as a DC-DC buck regulator includes a driver circuit that enables charge stored on the parasitic capacitance of a transistor switch to be transferred to a load capacitor. Hence, stored charge can be harvested for use by a load, thereby increasing efficiency of the regulator.

Abstract: An integrated circuit (IC) includes a power grid having first, through fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively, a voltage regulator, a reference voltage calibration circuit, a dual-rail sense circuit, and a voltage monitor circuit. The reference voltage calibration circuit receives the first supply, first ground, second supply, and second ground voltage signals and generates a reference voltage signal based on differences between voltage levels of the first supply and ground voltage signals, and the second supply and ground voltage signals. The voltage regulator regulates the first supply voltage signal based on the reference voltage signal and the second supply voltage signal. The dual-rail sense circuit generates a sense signal based on the second supply and ground voltage signals. The voltage monitor generates a voltage monitor signal based on the sense signal that indicates a state of the IC.

Abstract: In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.

Abstract: Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.

Abstract: In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.

Abstract: An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.

Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.

Abstract: Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.

Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.

Abstract: A voltage converter such as a DC-DC buck regulator includes a driver circuit that enables charge stored on the parasitic capacitance of a transistor switch to be transferred to a load capacitor. Hence, stored charge can be harvested for use by a load, thereby increasing efficiency of the regulator.

Abstract: A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

Abstract: A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.