Patents by Inventor Nishant Singh

Nishant Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160033567
    Abstract: In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 4, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Nishant Singh Thakur, Rakesh Pandey, Manmohan Rana
  • Patent number: 9252751
    Abstract: Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
    Type: Grant
    Filed: May 4, 2014
    Date of Patent: February 2, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nishant Singh Thakur, Rakesh Pandey, Manmohan Rana
  • Patent number: 9234936
    Abstract: In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: January 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC
    Inventors: Nishant Singh Thakur, Rakesh Pandey, Manmohan Rana
  • Publication number: 20150378385
    Abstract: An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Manmohan Rana, Rakesh Pandey, Nishant Singh Thakur
  • Patent number: 9214942
    Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: December 15, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Nishant Singh Thakur
  • Publication number: 20150318842
    Abstract: Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
    Type: Application
    Filed: May 4, 2014
    Publication date: November 5, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Nishant Singh Thakur, Rakesh Pandey, Manmohan Rana
  • Publication number: 20150236674
    Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.
    Type: Application
    Filed: February 17, 2014
    Publication date: August 20, 2015
    Inventor: Nishant Singh Thakur
  • Publication number: 20150222172
    Abstract: A voltage converter such as a DC-DC buck regulator includes a driver circuit that enables charge stored on the parasitic capacitance of a transistor switch to be transferred to a load capacitor. Hence, stored charge can be harvested for use by a load, thereby increasing efficiency of the regulator.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Inventor: Nishant Singh Thakur
  • Publication number: 20150149766
    Abstract: Systems and methods for facilitating authentication of an electronic device accessing plurality of mobile applications are disclosed. The system may receive a device public key and authentication information of the electronic device. The system may validate the authentication information to initiate a device session with the electronic device and create an authentication token signed with a server signature. The system may enable the electronic device to access a first mobile application based on the authentication information validated. Further, the system may receive the authentication token signed with a device signature. The system may authorize the authentication token by verifying the device signature and the server signature on the authentication token with a device public key and a server public key respectively. The system may then enable the electronic device to access the second mobile application using the authentication token authorized.
    Type: Application
    Filed: April 1, 2014
    Publication date: May 28, 2015
    Applicant: Tata Consultancy Services Limited
    Inventors: Kartikey Shukla, Nishant Singh, Kalidas Krishna Shetty, Shishir Tiwari, Nisha Yohannan
  • Patent number: 9020631
    Abstract: Disclosed are various embodiments for consolidating multiple pickings of an item to fulfill multiple shipments into a single picking of the multiple items. A determination is first made whether a metric representing a plurality of shipments exceeds a threshold, wherein individual ones of the plurality of shipments are mapped to corresponding ones of a plurality of item locations in a fulfillment center. The plurality of shipments are then remapped to an individual one of the plurality of item locations in response to a determination that the metric exceeds the threshold. Finally, a picking of the items is initiated.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 28, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Denis Bellavance, Michael Cy Wu, Robert James Wilson, Bryan Michael Psimas, Mona Mehrandish, Jacob Marshall Austin, Salman Hamid Ali, Nishant Singh, Fnu Arun Singhal
  • Patent number: 8890602
    Abstract: A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Samaksh Sinha, Manmohan Rana, Nishant Singh Thakur
  • Patent number: 8890495
    Abstract: A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Samaksh Sinha, Garima Sharda, Nishant Singh Thakur
  • Publication number: 20140203866
    Abstract: A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Inventors: Samaksh Sinha, Garima Sharda, Nishant Singh Thakur
  • Publication number: 20140197883
    Abstract: A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
    Type: Application
    Filed: January 16, 2013
    Publication date: July 17, 2014
    Inventors: Samaksh Sinha, Manmohan Rana, Nishant Singh Thakur
  • Publication number: 20140086803
    Abstract: A system for improving NOx reduction by incorporating an upstream treatment housing having a dual functionality catalyst that includes a diesel oxidation catalyst and a three-way catalyst, and which is positioned upstream of a main exhaust gas treatment system. The upstream treatment housing is positioned in relative close proximity to an exhaust turbine to prevent or minimize a reduction in exhaust gas temperature as the exhaust gas travels between the outlet of the turbine and the upstream treatment housing. By preventing such a reduction in exhaust gas temperature, the three way catalyst in the upstream treatment housing may operate at exhaust gas temperatures higher than those in main exhaust gas treatment system, which may allow for NOx conversion in the upstream treatment housing during certain cold operating or ambient conditions that is not typically attained in the main treatment system during such conditions.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: International Engine Intellectual Property Company, LLC
    Inventors: Carlos Luis Cattani, Michael Uchanski, Rogelio Rodiguez, Dileep Khadilkar, Nishant Singh, Joao P. Silva, Bradley Jay Adelman, Silpa Mandarapu, Shyam Santhanam
  • Patent number: 8651938
    Abstract: A simulated musical interface associated with a gaming machine enhances player excitement and interaction with the gaming machine. In one embodiment, the simulated musical interface is associated with a game in which the player uses the interface to play a simulated instrument on a gaming machine to affect, or apparently affect, the outcome of the game. As the player plays the simulated instrument via the simulated musical interface, indicia or graphical representations may be generated for a game of chance on a display associated with the gaming machine.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 18, 2014
    Assignee: Bally Gaming, Inc.
    Inventors: Barry Iremonger, Keshav Pitani, Loren T. Nelson, Rajaraman Ramachandran, Nishant Singh, Umashankar Chikkahonnaiah, Sandeep Surendran
  • Patent number: 8407985
    Abstract: In a method of determining hydrocarbon slip through a diesel oxidation catalyst for an engine having an electronic control module and an exhaust system having a diesel oxidation catalyst and a diesel particulate filter, the electronic control module receives data indicative of a temperature of a diesel oxidation catalyst input, a temperature of a diesel oxidation catalyst output, and a temperature of a diesel particulate filter output. An energy conversion ratio is calculated with the electronic control module using the data indicative of the temperature of the diesel oxidation catalyst input, the temperature of the diesel oxidation catalyst output, and the temperature of the diesel particulate filter output. The calculated energy conversion ratio is compared to stored energy conversion ratio in a memory accessed by the electronic control module.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: April 2, 2013
    Assignee: International Engine Intellectual Property Company, LLC
    Inventor: Nishant Singh
  • Patent number: 8381519
    Abstract: A method of controlling an engine exhaust temperature and an exhaust mass flow rate for stationary regeneration of an engine exhaust gas particulate filter of an engine. The method implements a feed forward control that sets an EGR valve position and an injection timing associated with the engine, and a sets an engine speed. The method implements a feed back control that sets a turbo waste gate position and an intake throttle position associated with the engine.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: February 26, 2013
    Assignee: International Engine Intellectual Property Company, LLC
    Inventors: Nishant Singh, Liquan Xu, Jeremy Ventura
  • Patent number: 8371923
    Abstract: A simulated musical interface associated with a gaming machine enhances player excitement and interaction with the gaming machine. In one embodiment, the simulated musical interface is associated with a game in which the player uses the interface to play a simulated instrument on a gaming machine to affect, or apparently affect, the outcome of the game. As the player plays the simulated instrument via the simulated musical interface, indicia or graphical representations may be generated for a game of chance on a display associated with the gaming machine.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 12, 2013
    Assignee: Bally Gaming, Inc.
    Inventors: Barry Iremonger, Keshav Pitani, Loren T. Nelson, Rajaraman Ramachandran, Nishant Singh, Umashankar Chikkahonnaiah, Sandeep Surendran
  • Patent number: 8266890
    Abstract: A method of determining a need to perform regeneration of a diesel particulate filter in a diesel engine exhaust predicts a soot load of a diesel particulate filter with a pressure change based soot load estimate based upon a pressure change across the diesel particulate filter at a first time and a second time. A restriction sensitivity for the diesel particulate filter is calculated based upon the pressure change across the diesel particulate filter at the first time and the second time. The method transitions from the pressure change based soot load estimate to a model based soot accumulation estimate of the soot load of the diesel particulate filter upon the restriction sensitivity falling below a predetermined threshold. Regeneration of the diesel particulate filter is requested after the estimated soot level reaches a preset level based upon the soot accumulation model.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: September 18, 2012
    Assignee: International Engine Intellectual Property Company, LLC
    Inventor: Nishant Singh