Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract: The present invention relates to a method for enabling hospitals or clinics to administer a dose of a drug to patients in need thereof while avoiding steps of manipulation, dilution, reconstitution, dispensing, sterilization, transfer, handling or compounding before intravenous administration. The present invention further relates to a perfusion system comprising different sets of perfusion containers, each container comprising a ready-to-infuse, stable, sterile, aqueous perfusion solution of a drug, wherein the set of perfusion containers alone or in combination provides for direct intravenous administration of a desired dose of the drug to a patient in need thereof, such that the delivered dose is equal to or within ±5% of the calculated dose.

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.