Patents by Inventor Nishith Rohatgi

Nishith Rohatgi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8298888
    Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Grant
    Filed: April 1, 2012
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
  • Publication number: 20120190165
    Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Application
    Filed: April 1, 2012
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Correale, JR., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
  • Patent number: 8188516
    Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
  • Patent number: 7904847
    Abstract: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Nishith Rohatgi, Benjamin John Bowers
  • Publication number: 20100155800
    Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Correale, JR., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
  • Patent number: 7728362
    Abstract: Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
  • Patent number: 7672188
    Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
  • Publication number: 20090210831
    Abstract: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.
    Type: Application
    Filed: February 18, 2008
    Publication date: August 20, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Correale, JR., Nishith Rohatgi, Benjamin John Bowers
  • Publication number: 20090154283
    Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Correale, JR., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
  • Publication number: 20070170553
    Abstract: Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Applicant: International Business Machines Corporation
    Inventors: Anthony Correale, Benjamin Bowers, Douglass Lamb, Nishith Rohatgi
  • Patent number: 6657912
    Abstract: A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit. A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Anthony Correale, Jr., Nishith Rohatgi