Patents by Inventor Nishith Rohatgi
Nishith Rohatgi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8298888Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: GrantFiled: April 1, 2012Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Publication number: 20120190165Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: ApplicationFiled: April 1, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Patent number: 8188516Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: GrantFiled: March 4, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Patent number: 7904847Abstract: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.Type: GrantFiled: February 18, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Nishith Rohatgi, Benjamin John Bowers
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Publication number: 20100155800Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: ApplicationFiled: March 4, 2010Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Patent number: 7728362Abstract: Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: GrantFiled: January 20, 2006Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
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Patent number: 7672188Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.Type: GrantFiled: December 12, 2007Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
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Publication number: 20090210831Abstract: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.Type: ApplicationFiled: February 18, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Nishith Rohatgi, Benjamin John Bowers
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Publication number: 20090154283Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
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Publication number: 20070170553Abstract: Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.Type: ApplicationFiled: January 20, 2006Publication date: July 26, 2007Applicant: International Business Machines CorporationInventors: Anthony Correale, Benjamin Bowers, Douglass Lamb, Nishith Rohatgi
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Patent number: 6657912Abstract: A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit. A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges.Type: GrantFiled: March 20, 2003Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Nishith Rohatgi