Patents by Inventor Nishkam Ravi
Nishkam Ravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9535826Abstract: There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.Type: GrantFiled: June 2, 2014Date of Patent: January 3, 2017Assignee: NEC CorporationInventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar, Bin Ren
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Patent number: 9201638Abstract: Various methods are provided directed to a compiler-guided software accelerator for iterative HADOOP® jobs. A method includes identifying intermediate data, generated by an iterative HADOOP® application, below a predetermined threshold size and used less than a predetermined threshold time period. The intermediate data is stored in a memory device. The method further includes minimizing input, output, and synchronization overhead for the intermediate data by selectively using at any given time any one of a Message Passing Interface and Distributed File System as a communication layer. The Message Passing Interface is co-located with the HADOOP® Distributed File System.Type: GrantFiled: June 21, 2013Date of Patent: December 1, 2015Assignee: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Abhishek Verma, Srimat T. Chakradhar
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Patent number: 9038088Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.Type: GrantFiled: March 1, 2012Date of Patent: May 19, 2015Assignee: NEC Laboratories America, Inc.Inventors: Rajat Phull, Srihari Cadambi, Nishkam Ravi, Srimat Chakradhar
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Patent number: 8997073Abstract: A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and accelerator memory, including adding relaxed semantics to a directive based language in the heterogenous computing for allowing a suggesting rather than specifying a parallel code region as an offloadable candidate, and identifying one or more offloadable tasks in a neighborhood of code region marked by the directive.Type: GrantFiled: April 25, 2014Date of Patent: March 31, 2015Assignee: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
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Publication number: 20150067225Abstract: There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.Type: ApplicationFiled: June 2, 2014Publication date: March 5, 2015Applicant: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar, Bin Ren
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Patent number: 8918770Abstract: A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.Type: GrantFiled: August 24, 2012Date of Patent: December 23, 2014Assignee: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
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Patent number: 8893103Abstract: Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a central processing unit (CPU) sub-part; executing the sampling sub-part with a processor to determine loop characteristics including memory- and processor-operations executed by the loop; identifying optimal split boundaries based on the loop characteristics such that the MIC sub-part will complete in a same amount of time when executed on a MIC processor as the CPU sub-part will take when executed on a CPU; and modifying the input source code to split the loop at the identified boundaries, such that the MIC sub-part is executed on a MIC processor and the CPU sub-part is concurrently executed on a CPU.Type: GrantFiled: July 12, 2013Date of Patent: November 18, 2014Assignee: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
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Publication number: 20140325495Abstract: A computer implemented method entails identifying code regions in an application from which offloadable tasks can be generated by a compiler for heterogenous computing system with processor and accelerator memory, including adding relaxed semantics to a directive based language in the heterogenous computing for allowing a suggesting rather than specifying a parallel code region as an offloadable candidate, and identifying one or more offloadable tasks in a neighborhood of code region marked by the directive.Type: ApplicationFiled: April 25, 2014Publication date: October 30, 2014Applicant: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
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Patent number: 8793675Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.Type: GrantFiled: December 24, 2010Date of Patent: July 29, 2014Assignee: Intel CorporationInventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
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Patent number: 8793674Abstract: A method for compiler-guided optimization of MapReduce type applications that includes applying transformations and optimizations to JAVA bytecode of an original application by an instrumenter which carries out static analysis to determine application properties depending on the optimization being performed and provides an output of optimized JAVA bytecode, and executing the application and analyzing generated trace and feeds information back into the instrumenter by a trace analyzer, the trace analyzer and instrumenter invoking each other iteratively and exchanging information through files.Type: GrantFiled: September 18, 2012Date of Patent: July 29, 2014Assignee: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Jun Liu, Srimat T. Chakradhar
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Publication number: 20140053131Abstract: Methods and systems for asynchronous offload to many-core coprocessors include splitting a loop in an input source code into a sampling sub-part, a many integrated core (MIC) sub-part, and a central processing unit (CPU) sub-part; executing the sampling sub-part with a processor to determine loop characteristics including memory- and processor-operations executed by the loop; identifying optimal split boundaries based on the loop characteristics such that the MIC sub-part will complete in a same amount of time when executed on a MIC processor as the CPU sub-part will take when executed on a CPU; and modifying the input source code to split the loop at the identified boundaries, such that the MIC sub-part is executed on a MIC processor and the CPU sub-part is concurrently executed on a CPU.Type: ApplicationFiled: July 12, 2013Publication date: February 20, 2014Inventors: Nishkam Ravi, Yi Yang, Srimat Chakradhar
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Publication number: 20140047422Abstract: Various methods are provided directed to a compiler-guided software accelerator for iterative HADOOP jobs. A method includes identifying intermediate data, generated by an iterative HADOOP application, below a predetermined threshold size and used less than a predetermined threshold time period. The intermediate data is stored in a memory device. The method further includes minimizing input, output, and synchronization overhead for the intermediate data by selectively using at any given time any one of a Message Passing Interface and Distributed File System as a communication layer. The Message Passing Interface is co-located with the HADOOP Distributed File System.Type: ApplicationFiled: June 21, 2013Publication date: February 13, 2014Inventors: Nishkam Ravi, Abhishek Verma, Srimat T. Chakradhar
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Publication number: 20130097593Abstract: A method for compiler-guided optimization of MapReduce type applications that includes applying transformations and optimizations to Java bytecode of an original application by an instrumenter which carries out static analysis to determine application properties depending on the optimization being performed and provides an output of optimized Java bytecode, and executing the application and analyzing generated trace and feeds information back into the instrumenter by a trace analyzer, the trace analyzer and instrumenter invoking each other iteratively and exchanging information through files.Type: ApplicationFiled: September 18, 2012Publication date: April 18, 2013Applicant: NEC Laboratories America, Inc.Inventors: Nishkam Ravi, Jun Liu, Srimat T. Chakradhar
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Publication number: 20130055225Abstract: A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.Type: ApplicationFiled: August 24, 2012Publication date: February 28, 2013Applicant: NEC LABORATORIES AMERICA, INC.Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
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Publication number: 20130055224Abstract: A system and method for compiling includes parsing code of an application stored in a computer readable storage medium to identify one or more parallelizable code portions. At least one parallelizable code portion is optimized by transforming offload construct code portions to provide an optimized application.Type: ApplicationFiled: August 24, 2012Publication date: February 28, 2013Applicant: NEC LABORATORIES AMERICA, INC.Inventors: Nishkam Ravi, Tao Bao, Ozcan Ozturk, Srimat Chakradhar
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Publication number: 20120233486Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.Type: ApplicationFiled: March 1, 2012Publication date: September 13, 2012Applicant: NEC Laboratories America, Inc.Inventors: Rajat Phull, Srihari Cadambi, Nishkam Ravi, Srimat Chakradhar
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Publication number: 20120167069Abstract: Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.Type: ApplicationFiled: December 24, 2010Publication date: June 28, 2012Inventors: Jin Lin, Nishkam Ravi, Xinmin Tian, John L. Ng, Renat V. Valiullin
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Patent number: 7743422Abstract: A portable device for connecting to a host information processing platform includes: a digital information storage medium storing an operating system image, secure data, applications, and system state of an owner of the portable device, wherein the medium is in read only mode until a set of tests are run on the host platform; and a platform validation program for: running the plurality of tests on the host computer to determine whether the host is safe, depending on the outcome of the tests, presenting the owner with a user-identifiable message, prompting the owner to enter decryption credentials, and receiving the decryption credentials. The portable device could also optionally include subsystems that provide additional functionality to the owner such as media playback, communications, and entertainment.Type: GrantFiled: August 21, 2006Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Chandrasekhar Narayanaswami, Mandayam Thondanur Raghunath, Nishkam Ravi, Marcel-Catalin Rosu
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Publication number: 20080046990Abstract: A portable device for connecting to a host information processing platform includes: a digital information storage medium storing an operating system image, secure data, applications, and system state of an owner of the portable device, wherein the medium is in read only mode until a set of tests are run on the host platform; and a platform validation program for: running the plurality of tests on the host computer to determine whether the host is safe, depending on the outcome of the tests, presenting the owner with a user-identifiable message, prompting the owner to enter decryption credentials, and receiving the decryption credentials. The portable device could also optionally include subsystems that provide additional functionality to the owner such as media playback, communications, and entertainment.Type: ApplicationFiled: August 21, 2006Publication date: February 21, 2008Applicant: International Business Machines CorporationInventors: Chandrasekhar Narayanaswami, Mandayam Thondanur Raghunath, Nishkam Ravi, Marcel-Catalin Rosu