Abstract: A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

Abstract: A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.

Abstract: A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.

Abstract: A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.

Abstract: A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.

Abstract: A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

Abstract: Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

Abstract: Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

Abstract: A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.

Abstract: A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.