Patents by Inventor Nishu Kohli
Nishu Kohli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535416Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.Type: GrantFiled: October 3, 2017Date of Patent: January 14, 2020Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Publication number: 20180025787Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.Type: ApplicationFiled: October 3, 2017Publication date: January 25, 2018Applicant: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Patent number: 9812219Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.Type: GrantFiled: March 6, 2015Date of Patent: November 7, 2017Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Patent number: 9324414Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.Type: GrantFiled: July 24, 2013Date of Patent: April 26, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nishu Kohli, Shishir Kumar
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Patent number: 9147453Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: GrantFiled: November 4, 2014Date of Patent: September 29, 2015Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Publication number: 20150179282Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Applicant: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Patent number: 9003255Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.Type: GrantFiled: July 1, 2011Date of Patent: April 7, 2015Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Publication number: 20150055400Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: ApplicationFiled: November 4, 2014Publication date: February 26, 2015Inventors: NISHU KOHLI, MUDIT BHARGAVA, SHISHIR KUMAR
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Patent number: 8963053Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.Type: GrantFiled: March 5, 2012Date of Patent: February 24, 2015Assignee: STMicroelectronics PVT. Ltd.Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
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Publication number: 20150029795Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.Type: ApplicationFiled: July 24, 2013Publication date: January 29, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nishu Kohli, Shishir Kumar
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Patent number: 8929115Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.Type: GrantFiled: November 30, 2011Date of Patent: January 6, 2015Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Patent number: 8913457Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.Type: GrantFiled: May 6, 2014Date of Patent: December 16, 2014Assignees: STMicroelectronics International N.V., STMicroelectronics SAInventors: Nishu Kohli, Robin M. Wilson
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Patent number: 8854902Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.Type: GrantFiled: May 18, 2012Date of Patent: October 7, 2014Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Patent number: 8854901Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.Type: GrantFiled: May 18, 2012Date of Patent: October 7, 2014Assignee: STMicroelectronics International N.V.Inventor: Nishu Kohli
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Publication number: 20140241102Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.Type: ApplicationFiled: May 6, 2014Publication date: August 28, 2014Applicants: STMicroelectronics International N.V., STMicroelectronics, SAInventors: Nishu KOHLI, Robin M. WILSON
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Patent number: 8730756Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.Type: GrantFiled: December 6, 2011Date of Patent: May 20, 2014Assignees: STMicroelectronics International N.V., STMicroelectronics, SAInventors: Nishu Kohli, Robin M. Wilson
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Patent number: 8681534Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).Type: GrantFiled: December 29, 2011Date of Patent: March 25, 2014Assignee: STMicroelectronics International N.V.Inventors: Nishu Kohli, Hiten Advani
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Publication number: 20130308397Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventor: Nishu Kohli
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Publication number: 20130308399Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventor: Nishu Kohli
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Publication number: 20130170288Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Nishu KOHLI, Hiten ADVANI