Abstract: A phase shifter circuit may include a multiple phase shifter cells (or cells) to selectively shift a phase of an input signal by a desired phase shift value. For example, each of the phase shifter cells may shift the phase of the input signal by a positive fractional phase shift value or a negative fractional phase shift value. The phase shifter cells may include circuitry to form an inductor-capacitor circuit to provide the negative fractional phase shift value and form a capacitor-inductor circuit to provide the positive fractional phase shift value. The phase shifter cells may receive control signals to form the inductor-capacitor circuit and the capacitor-inductor circuit. An electronic device may include multiple phase shifter circuits to adjust a phase of transmission signals and/or reception signals of phased array antennas.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

Abstract: Wireless circuitry is provided that includes a radio-frequency circuit having an input transistor and bias point selection circuitry configured to determine an optimal bias voltage for the input transistor. The bias point selection circuitry may include a replica transistor, a voltage generator configured to output one or more voltage levels to a gate terminal of the replica transistor, a current-to-voltage converter coupled to a source-drain terminal of the replica transistor, an analog-to-digital converter configured to receive analog voltages from the current-to-voltage converter and to output corresponding digital codes based on the received analog voltages, and associated control circuitry configured to receive the digital codes from the analog-to-digital converter and to adjust the voltage generator to output the optimal bias voltage based on the digital codes.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. Radio-frequency power amplifier circuitry may include an amplifier, an input transformer for coupling radio-frequency input signals to the amplifier, an active inductor load coupled to the input transformer, and a second order intermodulation generation circuit configured to generate and inject a second order intermodulation product into the input transformer. The injected second order intermodulation product can be used to cancel out unwanted third order intermodulation products generated by the amplifier, which reduces intermodulation distortion experienced by the amplifier circuitry.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. Radio-frequency power amplifier circuitry may include an amplifier, an input transformer for coupling radio-frequency input signals to the amplifier, an active inductor load coupled to the input transformer, and a second order intermodulation generation circuit configured to generate and inject a second order intermodulation product into the input transformer. The injected second order intermodulation product can be used to cancel out unwanted third order intermodulation products generated by the amplifier, which reduces intermodulation distortion experienced by the amplifier circuitry.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. Radio-frequency power amplifier circuitry may include an amplifier, an input transformer for coupling radio-frequency input signals to the amplifier, an active inductor load coupled to the input transformer, and a second order intermodulation generation circuit configured to generate and inject a second order intermodulation product into the input transformer. The injected second order intermodulation product can be used to cancel out unwanted third order intermodulation products generated by the amplifier, which reduces intermodulation distortion experienced by the amplifier circuitry.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include multiple amplifier stages. Current sharing or reuse may occur between two amplifier stages in the power amplifier via a current flow path between the two amplifier stages. A power supply voltage line may be connected to the current flow path and may provide the downstream amplifier stage with a supplemental supply current based on which the downstream amplifier stage can amplify a radio-frequency signal received from the upstream amplifier stage.

Abstract: Wireless circuitry can have an antenna connected to a transmitting amplifier and a receiving amplifier. The wireless circuitry may be operable in a transmit mode during which only the transmitting amplifier is active and in a receive mode during which only the receiving amplifier is active. The transmitting amplifier may be connected to the antenna via a balun and a radio-frequency coupler without an intervening switch that is enabled during the transmit mode and disabled during the receive mode. The transmitting amplifier may include input transistors, cascode transistors, first switches configured to selectively decouple gate terminals of the cascode transistors from a bias voltage, output capacitors, and second switches configured to selectively decouple the output capacitors from a ground line. The first and second switches are turned on during the transmit mode and are turned off during the receive mode to increase an output impedance of the transmitting amplifier.

Abstract: Wireless circuitry can have an antenna connected to a transmitting amplifier and a receiving amplifier. The wireless circuitry may be operable in a transmit mode during which only the transmitting amplifier is active and in a receive mode during which only the receiving amplifier is active. The transmitting amplifier may be connected to the antenna via a balun and a radio-frequency coupler without an intervening switch that is enabled during the transmit mode and disabled during the receive mode. The transmitting amplifier may include input transistors, cascode transistors, first switches configured to selectively decouple gate terminals of the cascode transistors from a bias voltage, output capacitors, and second switches configured to selectively decouple the output capacitors from a ground line. The first and second switches are turned on during the transmit mode and are turned off during the receive mode to increase an output impedance of the transmitting amplifier.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. Radio-frequency power amplifier circuitry may include an amplifier, an input transformer for coupling radio-frequency input signals to the amplifier, an active inductor load coupled to the input transformer, and a second order intermodulation generation circuit configured to generate and inject a second order intermodulation product into the input transformer. The injected second order intermodulation product can be used to cancel out unwanted third order intermodulation products generated by the amplifier, which reduces intermodulation distortion experienced by the amplifier circuitry.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more radio-frequency amplifiers for amplifying a radio-frequency signal. The radio-frequency amplifier may include input transistors cross-coupled with capacitance neutralization transistors and/or coupled to cascode transistors. One or more n-type gain adjustment transistors may be coupled to source terminals of the capacitance neutralization transistors. One or more p-type gain adjustment transistors may be coupled to source terminals of the cascode transistors. One or more processors in the electronic device can selectively activate one or more of the gain adjustment transistors to reduce the gain of the radio-frequency amplifier without degrading noise performance and without altering the in-band frequency response of the radio-frequency amplifier.

Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. Radio-frequency power amplifier circuitry may include an amplifier, an input transformer for coupling radio-frequency input signals to the amplifier, an active inductor load coupled to the input transformer, and a second order intermodulation generation circuit configured to generate and inject a second order intermodulation product into the input transformer. The injected second order intermodulation product can be used to cancel out unwanted third order intermodulation products generated by the amplifier, which reduces intermodulation distortion experienced by the amplifier circuitry.

Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.

Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.

Abstract: Disclosed wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses bi-directionally communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through a wired connection.

Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.

Abstract: Disclosed wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses bi-directionally communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through a wired connection.

Abstract: Disclosed wireless tunneling system includes two wireless tunneling apparatuses that communicate with each other through the wireless link. A local wireless tunneling apparatus is coupled to a local processing apparatus through a wired connection and a remote wireless tunneling apparatus is coupled to the remote processing apparatus through another wired connection. The two processing apparatuses bi-directionally communicate with each other through the wireless link using the two wireless tunneling apparatuses as if the two processing apparatuses were connected through a wired connection.

Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.