Patents by Inventor Nithin GOPINATH
Nithin GOPINATH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955984Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.Type: GrantFiled: May 31, 2022Date of Patent: April 9, 2024Assignee: Texas Instruments IncorporatedInventors: Viswanathan Nagarajan, Aniket Datta, Nithin Gopinath
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Publication number: 20240072820Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Sai Aditya Nurani, Rishi Soundararajan, Nithin Gopinath, Visvesvaraya Pentakota, Shagun Dusad
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Patent number: 11881867Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Publication number: 20230387933Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Viswanathan NAGARAJAN, Aniket DATTA, Nithin GOPINATH
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Publication number: 20230387932Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Narasimhan RAJAGOPAL, Nithin GOPINATH, Viswanathan NAGARAJAN, Neeraj SHRIVASTAVA, Visvesvaraya A. PENTAKOTA, Harshit MOONDRA, Abhinav CHANDRA
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Publication number: 20230344436Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Nithin Gopinath, Visvesvaraya A. Pentakota, Neeraj Shrivastava, Harshit Moondra
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Publication number: 20230033830Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Sthanunathan RAMAKRISHNAN, Nithin GOPINATH, Sai Aditya NURANI, Joseph Palackal MATHEW, Nagalinga Swamy Basayya AREMALLAPUR
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Patent number: 11569827Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.Type: GrantFiled: July 30, 2021Date of Patent: January 31, 2023Assignee: Texas Instruments IncorporatedInventors: Sthanunathan Ramakrishnan, Nithin Gopinath, Sai Aditya Nurani, Joseph Palackal Mathew, Nagalinga Swamy Basayya Aremallapur
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Publication number: 20220247420Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: ApplicationFiled: September 7, 2021Publication date: August 4, 2022Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Patent number: 10181107Abstract: A method, system, and computer program product for generating forecasts and replenishment plans. Some embodiments commence upon receiving point-of-sale data, then receiving distribution-level order data in a second data format. The first point-of-sale data comprises an item identifier and a first date or first date range, and the distribution-level order data comprises the item identifier and a second date or second date range. The originators of the order data are determined using address identifiers (e.g., network location identifiers). The received data is combined wherein at least a portion of the point-of-sale data is combined with at least a portion of the distribution-level order data to generate a combined forecast for the item. Further processing includes receiving an inventory model parameter and combining at least a portion of the first point-of-sale consumption data with at least a portion of the distribution-level order data to generate a replenishment plan for the item.Type: GrantFiled: June 25, 2014Date of Patent: January 15, 2019Assignee: Oracle International CorporationInventors: Nithin Gopinath, Kiran Saindane, Nadav Zivelin, Bart Feldman, Michael Liebson, Vikash Goyal, Nagappan Periakaruppan, Eytan E. Arkin
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Patent number: 10002364Abstract: A method, system, and computer program product for generating forecasts and replenishment plans. Some embodiments commence upon receiving point-of-sale data, then receiving distribution-level order data in a second data format. The first point-of-sale data comprises an item identifier and a first date or first date range, and the distribution-level order data comprises the item identifier and a second date or second date range. The originators of the order data are determined using address identifiers (e.g., network location identifiers). The received data is combined wherein at least a portion of the point-of-sale data is combined with at least a portion of the distribution-level order data to generate a combined forecast for the item. Further processing includes receiving an inventory model parameter and combining at least a portion of the first point-of-sale consumption data with at least a portion of the distribution-level order data to generate a replenishment plan for the item.Type: GrantFiled: June 25, 2014Date of Patent: June 19, 2018Assignee: Oracle International CorporationInventors: Nithin Gopinath, Kiran Saindane, Nadav Zivelin, Bart Feldman, Michael Liebson, Vikash Goyal, Nagappan Periakaruppan, Eytan E. Arkin
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Publication number: 20150379449Abstract: A method, system, and computer program product for generating forecasts and replenishment plans. Some embodiments commence upon receiving point-of-sale data, then receiving distribution-level order data in a second data format. The first point-of-sale data comprises an item identifier and a first date or first date range, and the distribution-level order data comprises the item identifier and a second date or second date range. The originators of the order data are determined using address identifiers (e.g., network location identifiers). The received data is combined wherein at least a portion of the point-of-sale data is combined with at least a portion of the distribution-level order data to generate a combined forecast for the item. Further processing includes receiving an inventory model parameter and combining at least a portion of the first point-of-sale consumption data with at least a portion of the distribution-level order data to generate a replenishment plan for the item.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Applicant: Oracle International CorporationInventors: Nithin GOPINATH, Kiran SAINDANE, Nadav ZIVELIN, Bart FELDMAN, Michael LIEBSON, Vikash GOYAL, Nagappan PERIAKARUPPAN, Eytan E. ARKIN
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Publication number: 20150379536Abstract: A method, system, and computer program product for generating forecasts and replenishment plans. Some embodiments commence upon receiving point-of-sale data, then receiving distribution-level order data in a second data format. The first point-of-sale data comprises an item identifier and a first date or first date range, and the distribution-level order data comprises the item identifier and a second date or second date range. The originators of the order data are determined using address identifiers (e.g., network location identifiers). The received data is combined wherein at least a portion of the point-of-sale data is combined with at least a portion of the distribution-level order data to generate a combined forecast for the item. Further processing includes receiving an inventory model parameter and combining at least a portion of the first point-of-sale consumption data with at least a portion of the distribution-level order data to generate a replenishment plan for the item.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Applicant: Oracle International CorporationInventors: Nithin GOPINATH, Kiran SAINDANE, Nadav ZIVELIN, Bart FELDMAN, Michael LIEBSON, Vikash GOYAL, Nagappan PERIAKARUPPAN, Eytan E. ARKIN