Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.

Abstract: A variety of methods/systems/apparatus/compositions are disclosed, including, in one embodiment, a downhole tool (for use in a borehole) having a mandrel, a sealing element including metal particles disposed about the mandrel, and a piston to move a containment component of the downhole tool in an axial direction to move the metal particles in the axial direction, thereby displacing the metal particles in a radial direction toward a borehole wall to expand the sealing element in the radial direction to form a seal between the downhole tool and the borehole wall.

Abstract: A variety of methods/systems/apparatus/compositions are disclosed, including, in one embodiment, a downhole tool (for use in a borehole) having a mandrel, a sealing element including metal particles disposed about the mandrel, and a piston to move a containment component of the downhole tool in an axial direction to move the metal particles in the axial direction, thereby displacing the metal particles in a radial direction toward a borehole wall to expand the sealing element in the radial direction to form a seal between the downhole tool and the borehole wall.

Abstract: Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the output of the circuit block. The prediction and gating circuitry include an output circuit configured to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit. The prediction and gating circuitry are inserted within the circuit design.

Abstract: Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.

Abstract: System and methods for implementations of sub-band correlation computation among all scheduled users to efficiently pair users across any group of Physical Resource Blocks.

Abstract: Systems and methods for contextual memory capture and recall are provided. The contextual memory capture and recall systems and methods help a user create, store, and recall memory information associated with an identified activity. The contextual memory capture and recall systems and methods are capable of identifying user activities where a memory inquiry may be desirable, creating a memory inquiry with a recommended memory action based on the activity, providing the memory inquiry to the user, and automatically linking an accepted memory action, along with any received memory information for the memory action, with the identified activity.

Abstract: A method is provided for enabling Narrowband Internet of Things (NBIOT) transport over fronthaul (FH) interface between distributed unit (DU) and radio unit (RU) for at least one of 4G Long Term Evolution (LTE) network and 5G New Radio (NR) network, which method includes: receiving, by an RU capable of at least one of NBIOT inband mode and NBIOT guardband mode, i) at least one of LTE and NR in-phase and quadrature (IQ) samples associated with a first endpoint, and ii) NBIOT ICI samples associated with a second endpoint; and configuring the RU functionality to be able to combine, in at least one of frequency domain and time domain, i) the at least one of LTE and NR in-phase and quadrature (IQ) samples associated with a first endpoint, and ii) the NBIOT ICI samples associated with a second endpoint.

Abstract: An Open Radio Access Network (O-RAN) system including a single frequency network (SFN) for handling signal transmissions involving a user equipment (UE) is provided, which system includes: a plurality of O-RAN radio units (O-RUs) configured to simultaneously send the same signal over the same frequency channel; and an O-RAN distributed unit (O-DU). The system is configured to filter out at least one of uplink (UL) and downlink (DL) signals associated with at least one of the plurality of O-RUs in the SFN based on one of signal power or signal-to-noise ratio (SNR). Signal paths of the O-RUs toward the O-DU are linked directly to the O-DU, and each of the O-RUs filters one of UL and DL signals based on a comparison to a predetermined signal power or SNR threshold. The O-DU controls DL transmission to only use the O-RUs whose UL signals were above the predetermined threshold.

Abstract: Systems and methods for contextual memory capture and recall are provided. The contextual memory capture and recall systems and methods help a user create, store, and recall memory information associated with an identified activity. The contextual memory capture and recall systems and methods are capable of identifying user activities where a memory inquiry may be desirable, creating a memory inquiry with a recommended memory action based on the activity, providing the memory inquiry to the user, and automatically linking an accepted memory action, along with any received memory information for the memory action, with the identified activity.

Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

Abstract: Disclosed methods and systems involve, prior to mapping logic of the module to a target integrated circuit (IC) technology, estimating total delay of a module of a circuit design and determining whether or not the module is timing critical based on the total delay of the module and a timing constraint. Also prior to mapping, the module is restructured for timing optimization in response to determining that the module is timing critical. In response to determining that the module is not timing critical, and prior to mapping, the module is restructured for area optimization. The elements of the module are then mapped to the circuit elements of the target IC technology, followed by place-and-route and generating implementation data for making an IC that implements the circuit design.

Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

Abstract: Systems and methods for contextual memory capture and recall are provided. The contextual memory capture and recall systems and methods help a user create, store, and recall memory information associated with an identified activity. The contextual memory capture and recall systems and methods are capable of identifying user activities where a memory inquiry may be desirable, creating a memory inquiry with a recommended memory action based on the activity, providing the memory inquiry to the user, and automatically linking an accepted memory action, along with any received memory information for the memory action, with the identified activity.

Abstract: An integrated circuit can include a processor configured to execute program code and a plurality of peripheral circuit blocks coupled to the processor. The plurality of peripheral circuit blocks are controlled by the processor as a master. The integrated circuit also can include a governor circuit coupled to the plurality of peripheral circuit blocks. The governor circuit is configured to monitor operation of the plurality of peripheral circuit blocks for known error states and, in response to detecting an occurrence of a selected known error state of the known error states in a selected peripheral circuit block of the plurality of peripheral circuit blocks, perform a predetermined action on the selected peripheral circuit block.

Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.

Abstract: Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.

Abstract: Automated system design for a programmable integrated circuit (IC) includes conducting, using computer hardware, a dialogue with a user, wherein the dialogue describes a user design for the programmable IC, extracting, using the computer hardware, a first plurality of features for the user design from the dialog, and generating, using the computer hardware, a design specification for the user design based on the first plurality of features. Using the computer hardware, a device configuration for the user design is generated based on the design specification. The device configuration is loadable within the programmable IC to implement the user design.

Abstract: Systems and methods for autonomously generating one or more images are disclosed. According to at least one embodiment, a method of autonomously generating one or more images includes: receiving, by a content server, an image having one or more characteristics rendering the image suitable for display at a device of a first breakpoint type; in response to receiving the image, autonomously deriving, by the content server, at least one image from the received image, the at least one derived image having one or more characteristics optimized for display at a device of a second breakpoint type different from the first breakpoint type; and controlling, by the content server, a display to display the received image and the at least one derived image.

Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.