Patents by Inventor Nithin Sathisan PODUVAL

Nithin Sathisan PODUVAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ERROR SAMPLER CIRCUIT
    Publication number: 20240163138
    Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Abishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO
  • METHODS AND APPARATUS TO PERFORM CML-TO-CMOS DESERIALIZATION
    Publication number: 20240113713
    Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Inventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
  • Error sampler circuit
    Patent number: 11916703
    Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Nithin Sathisan Poduval, Roland Nii Ofei Ribeiro
  • Methods and apparatus to perform CML-to-CMOS deserialization
    Patent number: 11888478
    Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 30, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
  • METHODS AND APPARATUS TO PERFORM CML-TO-CMOS DESERIALIZATION
    Publication number: 20230135422
    Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
  • ERROR SAMPLER CIRCUIT
    Publication number: 20230122240
    Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Abishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO
  • Error sampler circuit
    Patent number: 11575546
    Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Nithin Sathisan Poduval, Roland Nii Ofei Ribeiro
  • ERROR SAMPLER CIRCUIT
    Publication number: 20220286327
    Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventors: Abishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO