Patents by Inventor Nithya Ramakrishnan

Nithya Ramakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11892951
    Abstract: A key value (KV) store, a method thereof, and a storage system are provided herein. The KV store may include a key logger; and a processor configured to receive a first command for storing a first KV in the KV store, write a first value of the first KV to a first NAND page, generate an extent map for identifying the first memory page including the first value, write the extent map to a second memory page, append an entry for storing the first KV to the key logger, and update a device hashmap of the KV store to include a first key of the first KV, upon a threshold being met within the key logger.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: February 6, 2024
    Inventors: Kedar Shrikrishna Patwardhan, Nithya Ramakrishnan
  • Patent number: 11818046
    Abstract: A device is described. The device may include a network port to connect to a network. The device may include a first controller configured to send and receive a first communication across the network using the network port. The device may include storage for a controller record for the controller may store a congestion score, a congestion timestamp, and an uncongested timestamp. The device may also include storage for a device-wide record including at least a second congestion score and a second congestion timestamp for the first controller and a third congestion score and a third congestion timestamp for a second controller. The device-wide record may be based at least in part on the controller record. A throttle may limit a second communication of a second controller based at least in part on the device-wide record.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 14, 2023
    Inventors: Nithya Ramakrishnan, Caroline Diana Kahn, Thomas Edward Rainey, III
  • Publication number: 20230359377
    Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
  • Publication number: 20230281130
    Abstract: A key value (KV) store, a method thereof, and a storage system are provided herein. The KV store may include a key logger; and a processor configured to receive a first command for storing a first KV in the KV store, write a first value of the first KV to a first NAND page, generate an extent map for identifying the first memory page including the first value, write the extent map to a second memory page, append an entry for storing the first KV to the key logger, and update a device hashmap of the KV store to include a first key of the first KV, upon a threshold being met within the key logger.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Kedar Shrikrishna PATWARDHAN, Nithya RAMAKRISHNAN
  • Patent number: 11740815
    Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
  • Publication number: 20230054127
    Abstract: A system and method for storing data. In some embodiments, the method includes: receiving, by a persistent key-value storage device including a hash for mapping keys to value addresses, a first instruction, the first instruction being an instruction for accessing a first key, in a first key-value collection; and recording the first instruction in an instruction log of the persistent key-value storage device.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 23, 2023
    Inventors: Kedar Shrikrishna PATWARDHAN, Nithya RAMAKRISHNAN
  • Publication number: 20230054002
    Abstract: A system and method for lifecycle-aware persistent key-value storage. In some embodiments, the method includes: receiving a first modification instruction, for a first key; incrementing a device write counter for a persistent storage device; selecting a first block, from the persistent storage device, for the first key, based on a current value of the device write counter; and storing the first key and an associated first value in the first block.
    Type: Application
    Filed: October 28, 2021
    Publication date: February 23, 2023
    Inventors: Kedar Shrikrishna PATWARDHAN, Nithya RAMAKRISHNAN
  • Publication number: 20230017732
    Abstract: A key value (KV) store, a method thereof, and a storage system are provided herein. The KV store may include a key logger; and a processor configured to receive a first command for storing a first KV in the KV store, write a first value of the first KV to a first NAND page, generate an extent map for identifying the first memory page including the first value, write the extent map to a second memory page, append an entry for storing the first KV to the key logger, and update a device hashmap of the KV store to include a first key of the first KV, upon a threshold being met within the key logger.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 19, 2023
    Inventors: Kedar Shrikrishna PATWARDHAN, Nithya RAMAKRISHNAN
  • Patent number: 11507592
    Abstract: A method of adapting a first key-value store to a second key-value store may include determining a conversion strategy based on one or more characteristics of the first key-value store and one or more characteristics of the second key-value store, converting the second key-value store to a converted key-value store based on the conversion strategy, and mapping the first key-value store to the converted key-value store based on a mapping function. The converted key-value store may be accessed on-the-fly. A data storage system may include a key-value interface configured to provide access to a lower key-value store, and a key-value adapter coupled to the key-value interface and configured to adapt an upper key-value store to the lower key-value store, wherein the key-value adapter may be configured to adapt at least two different types of the upper key-value store to the lower key-value store.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 22, 2022
    Inventors: Zhengyu Yang, Thomas Edward Rainey, III, Michael Kurt Gehlen, Ping Terence Wong, Venkatraman Balasubramanian, Olufogorehan Adetayo Tunde-Onadele, Nithya Ramakrishnan, T. David Evans, Clay Mayers
  • Publication number: 20220239594
    Abstract: A device is described. The device may include a network port to connect to a network. The device may include a first controller configured to send and receive a first communication across the network using the network port. The device may include storage for a controller record for the controller may store a congestion score, a congestion timestamp, and an uncongested timestamp. The device may also include storage for a device-wide record including at least a second congestion score and a second congestion timestamp for the first controller and a third congestion score and a third congestion timestamp for a second controller. The device-wide record may be based at least in part on the controller record. A throttle may limit a second communication of a second controller based at least in part on the device-wide record.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 28, 2022
    Inventors: Nithya RAMAKRISHNAN, Caroline Diana KAHN, Thomas Edward RAINEY, III
  • Patent number: 11240294
    Abstract: A load balancing system includes: a centralized queue; a pool of resource nodes connected to the centralized queue; one or more processors; and memory coupled to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors to: monitor a queue status of the centralized queue to identify a bursty traffic period; calculate an index value for a load associated with the bursty traffic period; select a load balancing strategy based on the index value; distribute the load to the pool of resource nodes based on the load balancing strategy; observe a state of the pool of resource nodes in response to the load balancing strategy; calculate a reward based on the observed state; and adjust the load balancing strategy based on the reward.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkatraman Balasubramanian, Olufogorehan Adetayo Tunde-Onadele, Zhengyu Yang, Ping Terence Wong, Nithya Ramakrishnan, T. David Evans, Clay Mayers
  • Patent number: 11216190
    Abstract: A system and method for managing input output queue pairs. In some embodiments, the method includes calculating a system utilization ratio, the system utilization ratio being a ratio of: an arrival rate of input output requests, to a service rate; determining whether: the system utilization ratio has exceeded a first threshold utilization during a time period exceeding a first threshold length, and adding a new queue pair is expected to improve system performance; and in response to determining: that the system utilization ratio has exceeded the first threshold utilization during a time period exceeding the first threshold length, and that adding a new queue pair is expected to improve system performance: adding a new queue pair.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra G. Sampath, T. David Evans, Clay Mayers
  • Publication number: 20210389891
    Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
  • Patent number: 11144226
    Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers
  • Publication number: 20210124754
    Abstract: A method of adapting a first key-value store to a second key-value store may include determining a conversion strategy based on one or more characteristics of the first key-value store and one or more characteristics of the second key-value store, converting the second key-value store to a converted key-value store based on the conversion strategy, and mapping the first key-value store to the converted key-value store based on a mapping function. The converted key-value store may be accessed on-the-fly. A data storage system may include a key-value interface configured to provide access to a lower key-value store, and a key-value adapter coupled to the key-value interface and configured to adapt an upper key-value store to the lower key-value store, wherein the key-value adapter may be configured to adapt at least two different types of the upper key-value store to the lower key-value store.
    Type: Application
    Filed: January 30, 2020
    Publication date: April 29, 2021
    Inventors: Zhengyu YANG, Thomas Edward RAINEY, III, Michael Kurt GEHLEN, Ping Terence WONG, Venkatraman BALASUBRAMANIAN, Olufogorehan Adetayo TUNDE-ONADELE, Nithya RAMAKRISHNAN, T. David EVANS, Clay MAYERS
  • Publication number: 20210058453
    Abstract: A load balancing system includes: a centralized queue; a pool of resource nodes connected to the centralized queue; one or more processors; and memory coupled to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors to: monitor a queue status of the centralized queue to identify a bursty traffic period; calculate an index value for a load associated with the bursty traffic period; select a load balancing strategy based on the index value; distribute the load to the pool of resource nodes based on the load balancing strategy; observe a state of the pool of resource nodes in response to the load balancing strategy; calculate a reward based on the observed state; and adjust the load balancing strategy based on the reward.
    Type: Application
    Filed: December 6, 2019
    Publication date: February 25, 2021
    Inventors: Venkatraman Balasubramanian, Olufogorehan Adetayo Tunde-Onadele, Zhengyu Yang, Ping Terence Wong, Nithya Ramakrishnan, T. David Evans, Clay Mayers
  • Publication number: 20200387312
    Abstract: A system and method for managing input output queue pairs. In some embodiments, the method includes calculating a system utilization ratio, the system utilization ratio being a ratio of: an arrival rate of input output requests, to a service rate; determining whether: the system utilization ratio has exceeded a first threshold utilization during a time period exceeding a first threshold length, and adding a new queue pair is expected to improve system performance; and in response to determining: that the system utilization ratio has exceeded the first threshold utilization during a time period exceeding the first threshold length, and that adding a new queue pair is expected to improve system performance: adding a new queue pair.
    Type: Application
    Filed: August 9, 2019
    Publication date: December 10, 2020
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra G. Sampath, T. David Evans, Clay Mayers
  • Publication number: 20200326868
    Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 15, 2020
    Inventors: Zhengyu Yang, Nithya Ramakrishnan, Allen Russell Andrews, Sudheendra Grama Sampath, T. David Evans, Clay Mayers