Patents by Inventor Nitin Bansal

Nitin Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250061276
    Abstract: A system for interaction pattern recognition receives an input primary interaction and accesses clusters indicating interaction group patterns. Each cluster includes a respective primary interaction and secondary interactions linked to that primary interaction. Each cluster is identified by a respective non-fungible token.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 20, 2025
    Inventors: Nitin Bansal, Kapil Juneja, Rajalakshmi Arumugam, Kumaraguru Mohan, Venkatesh Polneedi, Anil Garg, Gaurav Kumar Kashyap
  • Patent number: 12085970
    Abstract: A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: September 10, 2024
    Assignee: Synopsys, Inc.
    Inventors: Ankit Agrawal, Sayan Adhikary, Nitin Bansal
  • Publication number: 20240257375
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for object recognition neural network for amodal center prediction. One of the methods includes receiving an image of an object captured by a camera. The image of the object is processed using an object recognition neural network that is configured to generate an object recognition output. The object recognition output includes data defining a predicted two-dimensional amodal center of the object, wherein the predicted two-dimensional amodal center of the object is a projection of a predicted three-dimensional center of the object under a camera pose of the camera that captured the image.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Inventors: Siddharth Mahendran, Nitin Bansal, Nitesh Sekhar, Manushree Gangwar, Khushi Gupta, Prateek Singhal
  • Patent number: 11989900
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for object recognition neural network for amodal center prediction. One of the methods includes receiving an image of an object captured by a camera. The image of the object is processed using an object recognition neural network that is configured to generate an object recognition output. The object recognition output includes data defining a predicted two-dimensional amodal center of the object, wherein the predicted two-dimensional amodal center of the object is a projection of a predicted three-dimensional center of the object under a camera pose of the camera that captured the image.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Magic Leap, Inc.
    Inventors: Siddharth Mahendran, Nitin Bansal, Nitesh Sekhar, Manushree Gangwar, Khushi Gupta, Prateek Singhal
  • Patent number: 11764765
    Abstract: A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: September 19, 2023
    Assignee: Synopsys, Inc.
    Inventors: Rahul Gupta, Nitin Bansal, Akhil Thotli, Manoj Kumar Reddy Puli
  • Publication number: 20230290132
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training an object recognition neural network using multiple data sources. One of the methods includes receiving training data that includes a plurality of training images from a first source and images from a second source. A set of training images are obtained from the training data. For each training image in the set of training images, contrast equalization is applied to the training image to generate a modified image. The modified image is processed using the neural network to generate an object recognition output for the modified image. A loss is determined based on errors between, for each training image in the set, the object recognition output for the modified image generated from the training image and ground-truth annotation for the training image. Parameters of the neural network are updated based on the determined loss.
    Type: Application
    Filed: July 28, 2021
    Publication date: September 14, 2023
    Inventors: Siddharth MAHENDRAN, Nitin BANSAL, Nitesh SEKHAR, Manushree GANGWAR, Khushi GUPTA, Prateek SINGHAL, Tarrence VAN AS, Adithya Shricharan Srinivasa RAO
  • Patent number: 11621704
    Abstract: An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 4, 2023
    Assignee: Synopsys, Inc.
    Inventors: Rahul Gupta, Nitin Bansal, Sriram Kumar Jayanthi
  • Publication number: 20220149822
    Abstract: An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 12, 2022
    Inventors: Rahul GUPTA, Nitin BANSAL, Sriram Kumar JAYANTHI
  • Publication number: 20220123738
    Abstract: A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 21, 2022
    Applicant: Synopsys, Inc.
    Inventors: Rahul Gupta, Nitin Bansal, Akhil Thotli, Manoj Kumar Reddy Puli
  • Publication number: 20210407125
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for object recognition neural network for amodal center prediction. One of the methods includes receiving an image of an object captured by a camera. The image of the object is processed using an object recognition neural network that is configured to generate an object recognition output. The object recognition output includes data defining a predicted two-dimensional amodal center of the object, wherein the predicted two-dimensional amodal center of the object is a projection of a predicted three-dimensional center of the object under a camera pose of the camera that captured the image.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Inventors: Siddharth Mahendran, Nitin Bansal, Nitesh Sekhar, Manushree Gangwar, Khushi Gupta, Prateek Singhal
  • Patent number: 10295416
    Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Nitin Bansal
  • Patent number: 10185338
    Abstract: A digital low drop-out regulator circuit includes transistor switches that are selectively actuated in response to a comparison of an output voltage at an output node to corresponding tap reference voltages. A dynamic reference voltage correction circuit operates to shift voltage levels of the tap reference voltages in response to a difference between the output voltage at the output node and an input reference voltage.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhirup Lahiri, Nitin Bansal, Shrestha Bansal
  • Publication number: 20180100774
    Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
    Type: Application
    Filed: October 10, 2016
    Publication date: April 12, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Nitin Bansal
  • Patent number: 9927828
    Abstract: According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 27, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Hemant Shukla, SaurabhKumar Singh, Nitin Bansal
  • Patent number: 9651958
    Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Bansal, Saurabh Kumar Singh, Hemant Shukla
  • Publication number: 20170060166
    Abstract: According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Hemant Shukla, SaurabhKumar Singh, Nitin Bansal
  • Publication number: 20160231758
    Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin Bansal, Saurabh Kumar Singh, Hemant Shukla
  • Patent number: 9395730
    Abstract: A method and apparatus are provided. The apparatus includes a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: July 19, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Saurabh Kumar Singh, Nitin Bansal, Kallol Chatterjee
  • Patent number: 9342085
    Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: May 17, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Hemant Shukla, Saurabh Kumar Singh, Nitin Bansal
  • Publication number: 20160103458
    Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 14, 2016
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Hemant Shukla, Saurabh Kumar Singh, Nitin Bansal