Abstract: A decoder includes circuitry for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. An embodiment of a decoder includes means for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.