Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.