Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.

Abstract: A network includes devices such as computers and the like, interconnected by switching nodes. The devices are identified by globally-unique identifiers, such as Ethernet MAC addresses or the like. At least some of the devices are configured to determine the topology of the network. In determining the network topology, a device operates in a series of iterations, in each iteration transmitting a request message over a path to determine whether an additional entity is present in the network. If an additional entity is present at the end of the path defined in the request message, the entity will generate a response, which is provided to the device. The device, on receiving the response, will add information concerning the entity to a network topology database, which it maintains to define the topology of the database. At least some of the devices, as they discover additional switching nodes in the network, will attempt to configure the switching nodes.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network.

Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.

Abstract: The present invention is directed to a method for arbitrating for control of a bus in a multiprocessor system. The multiprocessor system comprises a plurality of processors and a main memory coupled to one another by the bus, each processor including a cache memory accessible by the corresponding processor and in connection with transactions on the bus. The method includes the steps of generating requests for control of the bus and granting control of the bus in respect of one of the requests. The bus is monitored for preselected transaction activity on the bus; and an idle cycle is inserted on the bus upon monitoring the preselected transaction activity.

Abstract: The present invention is directed to a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to one another by a bus. The method includes the steps of providing caches of different sizes with a cache having a smallest size, and with each cache having an index fixed as a function of the size of the cache. For each exchange transaction, the number of bits of an index used to address a selected cache location are determined, and the upper bits of a memory address from a tag store location corresponding to the selected cache location are retrieved, where the retrieved upper address bits form an exchange address. In the event that the index of the selected cache location comprises more bits than the index of the cache having the fewest addressable locations, the excess bits of the index of the selected cache location are appended to the exchange address.

Abstract: The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

Abstract: A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a backup cache and a bus interface. The backup cache memory a first TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the backup cache memory. The primary cache memory includes a second TAG store comprising a plurality of address indicators and a plurality of VALID indicators, one address indicator and one VALID indicator for each of the data items currently contained in the primary cache memory. The interface includes a duplicate TAG store coupled to the primary cache memory, the duplicate TAG store consisting of a copy of the address indicators of the second TAG store. The bus interface is coupled to the processor, the backup cache memory and to the bus.

Abstract: A N-stage synchronizer for synchronizing asynchronous signals in a destination system's time domain. The synchronizer has N-stages with each stage having a series connected logic gate and flip-flop, and each of the N-stages are connected in series. Each logic gate has the output of the previous stage input thereto along with an ABORT signal. The ABORT signal when asserted blocks the synchronization of the asynchronous signal. The synchronizer permits a reduction in the latency associated with the synchronization process while not affecting reliability.

Abstract: A N-stage synchronizer for generating a synchronous signal that is derived from multiple sources. The synchronizer has an edge detector and N-1 stages for each asynchronous source signal. The outputs of the N-1 the synchronizer stages are processed according to an OR function. After the OR function, the merged asynchronous source signals are input to the shared last synchronizer stage. The output of the last synchronizer stage is the synchronous signal. The N-stage synchronizer reduces capacitance associated with the synchronizer and, therefore, lessens the time to assert or de-assert the synchronous signal, and reduces the time necessary to generate the synchronous signal.