Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

Abstract: Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection may be performed on the graph. For each cycle detected on the graph, the cycle may be broken by deleting the edge from the graph and ripping-up a portion of the routing solution corresponding to the deleted edge. The circuit design, or portion thereof, for which the routing solution was ripped up may be re-routed using an increased cost for a shared routing resource freed from the ripping-up.

Abstract: Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map to drivers of nets can be added to the compact DFG, where each group of the compact DFG is driven by a dedicated VDN. Connections between VDNs and load nodes through selected ones of the VBNs are created according to a plurality of constraints. The plurality of buffers are allocated to the nets based on the compact DFG as connected.

Abstract: Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map to drivers of nets can be added to the compact DFG, where each group of the compact DFG is driven by a dedicated VDN. Connections between VDNs and load nodes through selected ones of the VBNs are created according to a plurality of constraints. The plurality of buffers are allocated to the nets based on the compact DFG as connected.

Abstract: Embodiments herein describe techniques for preventing a stall when transmitting data between a producer and a consumer in the same integrated circuit (IC). A stall can occur when there is a split point and a convergence point between the producer and consumer. To prevent the stall, the embodiments herein adjust the latencies of one of the paths (or both paths) such that a maximum latency of the shorter path is greater than, or equal to, the minimum latency of the longer path. When this condition is met, this means the shortest path has sufficient buffers (e.g., a sufficient number of FIFOs and registers) to queue/store packets along its length so that a packet can travel along the longer path and reach the convergence point before the buffers in the shortest path are completely full (or just become completely full).

Abstract: Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

Abstract: The present disclosure relates to methods and apparatus for anonymously broadcasting locality based event information. More particularly, the present disclosure relates to broadcasting local event information from a portable broadcast device to multiple mobile devices, wherein the multiple mobile devices may be located within the vicinity of the local event or may subscribe to receiving event information about that locality.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.