Patents by Inventor Nitin Godiwala

Nitin Godiwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7773616
    Abstract: Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: August 10, 2010
    Assignee: SiCortex, Inc.
    Inventors: Matthew H. Reilly, Nitin Godiwala, Judson S. Leonard
  • Patent number: 7773618
    Abstract: Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: August 10, 2010
    Assignee: SiCortex, Inc.
    Inventors: Judson S. Leonard, Matthew H. Reilly, Nitin Godiwala
  • Patent number: 7773617
    Abstract: Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: August 10, 2010
    Assignee: SiCortex, Inc.
    Inventors: Nitin Godiwala, Judson S. Leonard, Matthew H. Reilly
  • Patent number: 7689856
    Abstract: A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: March 30, 2010
    Assignee: SiCortex, Inc.
    Inventor: Nitin Godiwala
  • Publication number: 20080109586
    Abstract: Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Nitin Godiwala, Judson S. Leonard, Matthew H. Reilly
  • Publication number: 20080109672
    Abstract: Large scale computing systems with multi-lane mesochronous data transfers among computer nodes. A large scale computing system includes a large plurality of computing nodes interconnected in a predefined topology. Each computing node is controlled by a corresponding clock signal, and the each clock signal has a mesochronous relationship to the clock signals on the other computing nodes. Each connection between nodes is a multi-lane connection, and each lane carries a serial stream of data that is mesochronously related to the other lanes. Each data lane is characterized relative to the other data lanes between the first and second node to determine relative delay in transmission between the first and second nodes. The transmission delays are equalized so that each data lane provides data for processing in the second clock domain in substantial synchronism with the other lanes.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Nitin Godiwala, Matthew H. Reilly
  • Publication number: 20080107105
    Abstract: Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Matthew H. Reilly, Nitin Godiwala, Judson S. Leonard
  • Publication number: 20080107116
    Abstract: A large-scale multiprocessor system with a link-level interconnect that provides in-order packet delivery. The method comprises transmitting, over a link in the defined interconnection topology, a sequence of packets in a defined order from a first node to a second node. The second node is an intermediate node in a route between the first and third node. At the first node, the transmitted packets are stored in a buffer. In response to an error in reception, the first node retrieves packets from the buffer and re-transmits them to the second node, beginning with the packet subsequent to the last packet in the sequence correctly received by the second node and continuing through the remainder of the sequence of packets.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Nitin Godiwala, Judson S. Leonard, Matthew H. Reilly, Lawrence C. Stewart
  • Publication number: 20080109671
    Abstract: A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventor: Nitin Godiwala
  • Publication number: 20080107106
    Abstract: Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Judson S. Leonard, Matthew H. Reilly, Nitin Godiwala