Patents by Inventor Nitin Jaiswal

Nitin Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260268996
    Abstract: Aspects presented herein may enable a device to detect memory faults during idle cycles of the memories or memory blocks using a clock gating logic to trigger memory self-tests, thereby improving safety coverage and early fault detection without affecting the functional logic of the system. In one aspect, a device identifies at least one block of at least one processor is in an idle mode, where the at least one block corresponds to a set of memories in the at least one processor. The device triggers, based on identification of the at least one block is in the idle mode, the at least one block to perform a self-test for checking whether one or more memories in the at least one block includes a fault. The device outputs an indication of the fault if the fault is detected in the one or more memories of the at least one block.
    Type: Application
    Filed: March 5, 2025
    Publication date: September 10, 2026
    Inventors: Amit DUGGAL, Sateeshkumar INJARAPU, Nitin JAISWAL
  • Publication number: 20260227441
    Abstract: A method for hardware-based periodic self-testing of safety mechanisms includes generating a test pattern after data processing has initiated in at least one block of a processor. The test pattern is provided to a safety mechanism. The safety mechanism generates a syndrome based on the test pattern. A fault in the safety mechanism is determined based on the syndrome.
    Type: Application
    Filed: February 4, 2025
    Publication date: August 6, 2026
    Inventors: Sateeshkumar INJARAPU, Amit DUGGAL, Nitin JAISWAL, Robert BATEMAN
  • Publication number: 20260212945
    Abstract: This disclosure provides systems, methods, and devices for memory systems that support detecting and tracking a quantity of errors in memory using a counter and indicating the detection and quantity of errors using an interrupt flag. In a first aspect, a method includes, at a hardware of a memory system detecting one or more errors at a memory. The method includes counting a quantity of the one or more errors until the quantity is equal to or greater than a threshold quantity of errors. The method includes recording the quantity of errors and an error type in an error log. The method includes transmitting an indication that the quantity of errors of the memory is equal to or greater than the threshold. Other aspects and features are also claimed and described.
    Type: Application
    Filed: January 21, 2025
    Publication date: July 23, 2026
    Inventors: Ishwarya Arumugam, Sateeshkumar Injarapu, Manish Kumar Saxena, Amit Duggal, Nitin Jaiswal
  • Publication number: 20260064546
    Abstract: A method includes detecting a functional safety fault and determining whether the functional safety fault is a transient fault or a permanent fault. The method further includes identifying a scalable block of a processing unit from which the functional safety fault occurred in response to the functional safety fault being determined to be a permanent fault. The method optionally includes power collapsing the scalable block. The method also includes notifying a scheduler to prevent the scheduler from scheduling future workloads to the scalable block.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 5, 2026
    Inventors: Amit DUGGAL, Sateeshkumar INJARAPU, Nitin JAISWAL
  • Publication number: 20260059276
    Abstract: Aspects presented herein relate to methods and devices for communication including an apparatus, e.g., a vehicle. The apparatus may initialize a set-up for at least one memory based on a redundancy correction for the at least one memory being completed. The apparatus may also determine whether the initialization of the set-up for the at least one memory is completed. The apparatus may also initiate a performance of at least one workload based on the initialization of the set-up for the at least one memory being completed.
    Type: Application
    Filed: August 21, 2024
    Publication date: February 26, 2026
    Inventors: Pragya NIGAM, Sateeshkumar INJARAPU, Manish Kumar SAXENA, Amit DUGGAL, Nitin JAISWAL
  • Publication number: 20260031171
    Abstract: Aspects of the disclosure are directed to deterministic memory initialization. In accordance with one aspect, the disclosure includes initializing a first current memory address in a plurality of memories to a first memory address using a plurality of shared built-in self-test (BIST) resources; writing a first deterministic pattern to a first memory data word specified by the first current memory address using the plurality of shared BIST resources; and incrementing the first current memory address to a first subsequent memory address using the plurality of shared BIST resources.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 29, 2026
    Inventors: Swetashree MISHRA, Ankit SHAMBHU, Sateeshkumar INJARAPU, Amit DUGGAL, Nitin JAISWAL
  • Patent number: 12518846
    Abstract: An error correction code (ECC) test system and method are provided that test ECC logic for faults, preferably at power on before a workload is being processed. If the ECC logic fails the test, preferably an interrupt is issued indicating that the ECC logic is faulty and the corresponding ECC fault signature is reported in a status register of the system as part of a consolidated system report.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: January 6, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Sateeshkumar Injarapu, Amit Duggal, Manish Kumar Saxena, Nitin Jaiswal
  • Publication number: 20260003727
    Abstract: Aspects of the disclosure are directed to dynamic error correction coding (ECC) disable control. In accordance with one aspect, the disclosure includes assigning each of a plurality of control status registers (CSRs) to each of a plurality of memory groups referenced by a group index to an indicator for error correction coding (ECC) disablement; and performing a dynamic ECC disablement for a plurality of data words for writing to one of the plurality of memory groups according to the indicator in an assigned each of the plurality of CSRs.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Inventors: Sateeshkumar INJARAPU, Amit DUGGAL, Manish Kumar SAXENA, Nitin JAISWAL, Ishwarya ARUMUGAM
  • Patent number: 12493514
    Abstract: Methods and apparatuses directed to memory fault detection mechanisms within die architectures. In some examples, a die package includes decoder logic that receives multiple data words, and a first error correcting code for each of the data words. The decoder logic generates, for each of the data words, a second error correcting code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error status based on the first error correcting code and the second error correcting code that corresponds to each of the data words. The die package also includes error generation logic that receives the error status for the data words from the decoder logic, and generates error data based on a combination of the error statuses for the data words. The error generation logic can store the error data in a memory device.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: December 9, 2025
    Assignee: Qualcomm Incorporated
    Inventors: Sateeshkumar Injarapu, Manish Kumar Saxena, Amit Duggal, Nitin Jaiswal
  • Publication number: 20250245100
    Abstract: A method for managing a plurality of imaging devices in a vehicle includes determining that a change of data security mode is indicated for frames of image data transmitted over a first data communication link, determining whether a sensor management system has sufficient processing capacity to support the change of data security mode, increasing the processing capacity of the sensor management system by modifying data security settings for at least one other data communication link when the processing capacity of the sensor management system is insufficient to support the change of data security mode, and initiating the change of data security mode when the sensor management system has sufficient processing capacity to support the change of data security mode. The change of data security mode may include a change from an application-based to a link-based data security mode or a change from the link-based to the application-based data security mode.
    Type: Application
    Filed: January 25, 2024
    Publication date: July 31, 2025
    Inventors: Sateeshkumar INJARAPU, Amit DUGGAL, Manish Kumar SAXENA, Nitin JAISWAL
  • Patent number: 12373291
    Abstract: A method for managing a plurality of imaging devices in a vehicle includes determining that a change of data security mode is indicated for frames of image data transmitted over a first data communication link, determining whether a sensor management system has sufficient processing capacity to support the change of data security mode, increasing the processing capacity of the sensor management system by modifying data security settings for at least one other data communication link when the processing capacity of the sensor management system is insufficient to support the change of data security mode, and initiating the change of data security mode when the sensor management system has sufficient processing capacity to support the change of data security mode. The change of data security mode may include a change from an application-based to a link-based data security mode or a change from the link-based to the application-based data security mode.
    Type: Grant
    Filed: January 25, 2024
    Date of Patent: July 29, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Sateeshkumar Injarapu, Amit Duggal, Manish Kumar Saxena, Nitin Jaiswal
  • Publication number: 20250103420
    Abstract: Methods and apparatuses directed to memory fault detection mechanisms within die architectures. In some examples, a die package includes decoder logic that receives multiple data words, and a first error correcting code for each of the data words. The decoder logic generates, for each of the data words, a second error correcting code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error status based on the first error correcting code and the second error correcting code that corresponds to each of the data words. The die package also includes error generation logic that receives the error status for the data words from the decoder logic, and generates error data based on a combination of the error statuses for the data words. The error generation logic can store the error data in a memory device.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Sateeshkumar INJARAPU, Manish Kumar SAXENA, Amit DUGGAL, Nitin JAISWAL
  • Patent number: 12181958
    Abstract: Various embodiments include methods and devices for error capturing implemented in a computing device. Embodiments may include receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger, including an error data for a memory of a processor having an identification of at least one faulty bit of the memory. Embodiments may include receiving a plurality of requests from a plurality of error capture modules for the processor at an error selection module for the processor, and retrieving an error data from an error capture module by the error selection module in response to a request from the error capture module being ordered prior to another request from another error capture module. Embodiments may include sending the error data to the error logger, and storing the error data at the error logger in an order relative to another error data.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: December 31, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Sateeshkumar Injarapu, Manish Kumar Saxena, Amit Duggal, Nitin Jaiswal
  • Publication number: 20240428876
    Abstract: An error correction code (ECC) test system and method are provided that test ECC logic for faults, preferably at power on before a workload is being processed. If the ECC logic fails the test, preferably an interrupt is issued indicating that the ECC logic is faulty and the corresponding ECC fault signature is reported in a status register of the system as part of a consolidated system report.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Sateeshkumar INJARAPU, Amit DUGGAL, Manish Kumar SAXENA, Nitin JAISWAL
  • Publication number: 20240211336
    Abstract: Various embodiments include methods and devices for error capturing implemented in a computing device. Embodiments may include receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger, including an error data for a memory of a processor having an identification of at least one faulty bit of the memory. Embodiments may include receiving a plurality of requests from a plurality of error capture modules for the processor at an error selection module for the processor, and retrieving an error data from an error capture module by the error selection module in response to a request from the error capture module being ordered prior to another request from another error capture module. Embodiments may include sending the error data to the error logger, and storing the error data at the error logger in an order relative to another error data.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Inventors: Sateeshkumar INJARAPU, Manish Kumar SAXENA, Amit Duggal, Nitin Jaiswal
  • Patent number: 11218490
    Abstract: Techniques for enrolling a user in an organization directory include receiving a first request from a first user for inclusion in the directory configured to facilitate access to a collaboration application, the first request including a least a first user profile item for the first user; generating a first user account for the user assigned a first set of permissions and including a first user profile listing the first user profile item; providing a first level of access to the directory; receiving a second request from a second user transitioning the first user account from the first set of permissions to a second, broader set of permissions; verifying a first user identity for the first user based on the second request; assigning the first user account the second set of permissions; automatically updating the directory; and providing a second level of access to the directory to the first user.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: January 4, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Teekam Chand Goyal, Deepak Pratinidhi, Rajiv Kumar, Prashant Gupta, Rohit Bhatia, Rakesh Midha, Ashutosh Tripathi, Nitin Jaiswal, Vinay Kumar
  • Publication number: 20200322347
    Abstract: Techniques for enrolling a user in an organization directory include receiving a first request from a first user for inclusion in the directory configured to facilitate access to a collaboration application, the first request including a least a first user profile item for the first user; generating a first user account for the user assigned a first set of permissions and including a first user profile listing the first user profile item; providing a first level of access to the directory; receiving a second request from a second user transitioning the first user account from the first set of permissions to a second, broader set of permissions; verifying a first user identity for the first user based on the second request; assigning the first user account the second set of permissions; automatically updating the directory; and providing a second level of access to the directory to the first user.
    Type: Application
    Filed: September 2, 2019
    Publication date: October 8, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Teekam Chand Goyal, Deepak Pratinidhi, Rajiv Kumar, Prashant Gupta, Rohit Bhatia, Rakesh Midha, Ashutosh Tripathi, Nitin Jaiswal, Vinay Kumar
  • Patent number: 10404631
    Abstract: A messaging system comprising: computer storage holding messaging accounts for users of the messaging system, each comprising a user identifier of a first type; an account manager for managing the messaging accounts; a group manager configured to grant participant users access to messaging groups by creating, in the computer storage, associations between the messaging groups and the messaging accounts of the participant users; a group messaging service configured for use in transmitting and receiving messages, in each of the plurality of messaging groups, between the participant users granted access to that messaging group, using the user identifiers of the first type in their messaging accounts.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Teekam Chand Goyal, Nitin Jaiswal, Rajiv Kumar, Prashant Gupta, Deepak Pratinidhi, Arun Rajappa, Apoorv Seth
  • Publication number: 20180205676
    Abstract: A messaging system comprising: computer storage holding messaging accounts for users of the messaging system, each comprising a user identifier of a first type; an account manager for managing the messaging accounts; a group manager configured to grant participant users access to messaging groups by creating, in the computer storage, associations between the messaging groups and the messaging accounts of the participant users; a group messaging service configured for use in transmitting and receiving messages, in each of the plurality of messaging groups, between the participant users granted access to that messaging group, using the user identifiers of the first type in their messaging accounts.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 19, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Teekam Chand Goyal, Nitin Jaiswal, Rajiv Kumar, Prashant Gupta, Deepak Pratinidhi, Arun Rajappa, Apoorv Seth