Patents by Inventor Nitin Kabra

Nitin Kabra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11893258
    Abstract: A method disclosed herein includes storing a data heat map in local cache of a non-volatile memory express (NVME) controller associated with an NVME device, configuring an asynchronous event notification command in a submission queue associated with the NVME device, generating a request for data migration notification to host based on the data heat map, and communicating the data migration notification to a host using the asynchronous event notification command.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: February 6, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kabra, Sneha Wagh
  • Publication number: 20220261172
    Abstract: A method disclosed herein includes storing a data heat map in local cache of a non-volatile memory express (NVME) controller associated with an NVME device, configuring an asynchronous event notification command in a submission queue associated with the NVME device, generating a request for data migration notification to host based on the data heat map, and communicating the data migration notification to a host using the asynchronous event notification command.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Nitin KABRA, Sneha WAGH
  • Patent number: 11334274
    Abstract: A method disclosed herein includes storing a data heat map in local cache of a non-volatile memory express (NVME) controller associated with an NVME device, configuring an asynchronous event notification command in a submission queue associated with the NVME device, generating a request for data migration notification to host based on the data heat map, and communicating the data migration notification to a host using the asynchronous event notification command.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: May 17, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kabra, Sneha Wagh
  • Patent number: 10802753
    Abstract: Implementations disclosed herein include a storage system including a plurality of storage devices, wherein each of the plurality of storage devices includes compute resources, memory resources, and a storage device controller configured to perform application-specific data management operations using the compute resources and the memory resources of the storage device, and a storage system controller configured to distribute a workload across the plurality of storage devices based on a capability of each of the plurality of storage devices during an IDLE state. The capability of each of the plurality of storage devices may be specifications, current availability, and performance history of each of the plurality of storage devices. In some implementations, each of the plurality of storage devices communicate with each other via a peer-to-peer networking communications protocol (e.g., NVme, NVMof, PCIe, Ethernet, etc.).
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 13, 2020
    Assignee: Seagate Technology LLC
    Inventors: Nitin Kabra, Manish Sharma, Rajesh Bhagwat, Sneha Wagh, Nilesh Govande
  • Publication number: 20190250845
    Abstract: A method disclosed herein includes storing a data heat map in local cache of a non-volatile memory express (NVME) controller associated with an NVME device, configuring an asynchronous event notification command in a submission queue associated with the NVME device, generating a request for data migration notification to host based on the data heat map, and communicating the data migration notification to a host using the asynchronous event notification command.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 15, 2019
    Inventors: Nitin Kabra, Sneha Wagh
  • Publication number: 20190250852
    Abstract: Implementations disclosed herein include a storage system including a plurality of storage devices, wherein each of the plurality of storage devices includes compute resources, memory resources, and a storage device controller configured to perform application-specific data management operations using the compute resources and the memory resources of the storage device, and a storage system controller configured to distribute a workload across the plurality of storage devices based on a capability of each of the plurality of storage devices during an IDLE state. The capability of each of the plurality of storage devices may be specifications, current availability, and performance history of each of the plurality of storage devices. In some implementations, each of the plurality of storage devices communicate with each other via a peer-to-peer networking communications protocol (e.g., NVme, NVMof, PCIe, Ethernet, etc.).
    Type: Application
    Filed: February 15, 2018
    Publication date: August 15, 2019
    Inventors: Nitin Kabra, Manish Sharma, Rajesh Bhagwat, Sneha Wagh, Nilesh Govande
  • Patent number: 8539135
    Abstract: A system and method for reducing overall connection latencies in a SAS expander is disclosed. The SAS expander includes a plurality of ports and a route lookup table configured for providing a central resource for routing information for the ports. The SAS expander also includes a plurality of connection history caches (CHCs) associated with the ports, each CHC is configured for storing at least one successfully established connection record. Upon receiving a connection request at a particular port, that particular port may determine whether a matching connection record for the connection request is stored in its corresponding CHC. If the matching connection record is stored in its corresponding CHC, a connection may be established in response to the connection request based on the matching connection record. However, if no matching connection record is found in its corresponding CHC, the connection may be established utilizing the route lookup table.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: September 17, 2013
    Assignee: LSI Corporation
    Inventors: Nitin Kabra, Gurvinder Singh
  • Publication number: 20120290762
    Abstract: A system and method for reducing overall connection latencies in a SAS expander is disclosed. The SAS expander includes a plurality of ports and a route lookup table configured for providing a central resource for routing information for the ports. The SAS expander also includes a plurality of connection history caches (CHCs) associated with the ports, each CHC is configured for storing at least one successfully established connection record. Upon receiving a connection request at a particular port, that particular port may determine whether a matching connection record for the connection request is stored in its corresponding CHC. If the matching connection record is stored in its corresponding CHC, a connection may be established in response to the connection request based on the matching connection record. However, if no matching connection record is found in its corresponding CHC, the connection may be established utilizing the route lookup table.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Applicant: LSI CORPORATION
    Inventors: Nitin Kabra, Gurvinder Singh
  • Publication number: 20110099304
    Abstract: The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).
    Type: Application
    Filed: July 22, 2005
    Publication date: April 28, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Chee Y. Ng, Nitin Kabra