Abstract: A multi-mode pulse width modulation (PWM) controller for a buck switching regulator includes a multi-mode PWM control circuit where the PWM control circuit is configured to operate in one of multiple control schemes selectable by a mode select signal. In one embodiment, the multi-mode PWM control circuit incorporates a peak current mode control scheme, a voltage mode control scheme, and a valley current mode control scheme. In another embodiment, the multi-mode PWM control circuit further incorporates a constant ON-time control scheme.

Abstract: A multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit. The phase control circuit is configured to receive a single phase PWM clock signal and generate N clock signals in N phases. Each of the N power cells includes a pair of power switches, gate drivers, a control circuit receiving one of the N clock signals and generating gate drive signals for the gate drivers, and an inductor. The current sharing control circuit is configured to assess the inductor current at the inductor of the N power cells and to generate duty cycle control signals for the N power cells. The duty cycle control signals are applied to the control circuits to adjust the duty cycle of one or more clock signals supplied to the power cells to balance a current loading among the N power cells.

Abstract: A multi-mode pulse width modulation (PWM) controller for a buck switching regulator includes a multi-mode PWM control circuit where the PWM control circuit is configured to operate in one of multiple control schemes selectable by a mode select signal. In one embodiment, the multi-mode PWM control circuit incorporates a peak current mode control scheme, a voltage mode control scheme, and a valley current mode control scheme. In another embodiment, the multi-mode PWM control circuit further incorporates a constant ON-time control scheme.

Abstract: A multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit. The phase control circuit is configured to receive a single phase PWM clock signal and generate N clock signals in N phases. Each of the N power cells includes a pair of power switches, gate drivers, a control circuit receiving one of the N clock signals and generating gate drive signals for the gate drivers, and an inductor. The current sharing control circuit is configured to assess the inductor current at the inductor of the N power cells and to generate duty cycle control signals for the N power cells. The duty cycle control signals are applied to the control circuits to adjust the duty cycle of one or more clock signals supplied to the power cells to balance a current loading among the N power cells.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.