Patents by Inventor Nitin Kumar Agarwal
Nitin Kumar Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220210056Abstract: A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Applicant: Arm LimitedInventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade
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Patent number: 11329690Abstract: The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.Type: GrantFiled: February 9, 2021Date of Patent: May 10, 2022Assignee: Arm LimitedInventors: Narayana Sri Harsha Gade, Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
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Patent number: 11310169Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.Type: GrantFiled: January 19, 2021Date of Patent: April 19, 2022Assignee: Arm LimitedInventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Nitin Kumar Agarwal, Anup Gangwar, Narayana Sri Harsha Gade, Ravishankar Sreedharan
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Patent number: 11283729Abstract: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.Type: GrantFiled: November 10, 2020Date of Patent: March 22, 2022Assignee: Arm LimitedInventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Ravishankar Sreedharan
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Patent number: 11194950Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.Type: GrantFiled: October 21, 2020Date of Patent: December 7, 2021Assignee: Arm LimitedInventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade
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Patent number: 11050672Abstract: The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.Type: GrantFiled: July 22, 2019Date of Patent: June 29, 2021Assignee: Arm LimitedInventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
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Publication number: 20210168038Abstract: The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Applicant: Arm LimitedInventors: Narayana Sri Harsha Gade, Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
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Publication number: 20210160194Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.Type: ApplicationFiled: January 19, 2021Publication date: May 27, 2021Applicant: Arm LimitedInventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Nitin Kumar Agarwal, Anup Gangwar, Narayana Sri Harsha Gade, Ravishankar Sreedharan
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Publication number: 20210058289Abstract: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Applicant: Arm LimitedInventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Ravishankar Sreedharan
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Publication number: 20210036967Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Applicant: Arm LimitedInventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade
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Publication number: 20210029045Abstract: The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.Type: ApplicationFiled: July 22, 2019Publication date: January 28, 2021Applicant: Arm LimitedInventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
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Patent number: 10817627Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.Type: GrantFiled: July 22, 2019Date of Patent: October 27, 2020Assignee: Arm LimitedInventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
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Patent number: 10791045Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.Type: GrantFiled: February 20, 2019Date of Patent: September 29, 2020Assignee: Arm LimitedInventors: Nitin Kumar Agarwal, Zheng Xu, Anup Gangwar
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Patent number: 10783286Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.Type: GrantFiled: July 22, 2019Date of Patent: September 22, 2020Assignee: Arm LimitedInventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
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Publication number: 20200267073Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.Type: ApplicationFiled: February 20, 2019Publication date: August 20, 2020Applicant: Arm LimitedInventors: Nitin Kumar Agarwal, Zheng Xu, Anup Gangwar
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Publication number: 20200134127Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data hanType: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: Anup GANGWAR, Nitin Kumar AGARWAL, Honnahuggi Harinath Venkata Naga Ambica PRASAD
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Patent number: 10635774Abstract: A computer-method is provided for designing a router network to connect components of an integrated circuit, where the router network comprises a plurality of connected data routing elements. The method comprises generating an undirected graph to represent a mesh of candidate router elements, where the candidate data routing elements are positioned dependent on at least one characteristic of the integrated circuit. The undirected graph comprises a node to represent each candidate data routing element and an edge to represent each connection between the candidate data routing elements.Type: GrantFiled: January 30, 2019Date of Patent: April 28, 2020Assignee: Arm LimitedInventors: Anup Gangwar, Nitin Kumar Agarwal
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Patent number: 10628626Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data hanType: GrantFiled: October 25, 2018Date of Patent: April 21, 2020Assignee: Arm LimitedInventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad
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Publication number: 20190266308Abstract: A computer-method is provided for designing a router network to connect components of an integrated circuit, where the router network comprises a plurality of connected data routing elements. The method comprises generating an undirected graph to represent a mesh of candidate router elements, where the candidate data routing elements are positioned dependent on at least one characteristic of the integrated circuit. The undirected graph comprises a node to represent each candidate data routing element and an edge to represent each connection between the candidate data routing elements.Type: ApplicationFiled: January 30, 2019Publication date: August 29, 2019Inventors: Anup GANGWAR, Nitin Kumar AGARWAL
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Patent number: 10318243Abstract: A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domainsType: GrantFiled: September 21, 2017Date of Patent: June 11, 2019Assignee: ARM LimitedInventors: Anup Gangwar, Nitin Kumar Agarwal