Patents by Inventor Nitin Kumar Chhabra
Nitin Kumar Chhabra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10896721Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.Type: GrantFiled: January 17, 2020Date of Patent: January 19, 2021Assignee: SEAGATE TECHNOLOGY LLCInventor: Nitin Kumar Chhabra
-
Patent number: 10691190Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.Type: GrantFiled: June 26, 2017Date of Patent: June 23, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar
-
Publication number: 20200152254Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Inventor: Nitin Kumar Chhabra
-
Patent number: 10621387Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.Type: GrantFiled: May 30, 2018Date of Patent: April 14, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar Chhabra, Rohit Halba, Shrikrishna Nana Mehetre
-
Patent number: 10594314Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.Type: GrantFiled: October 17, 2017Date of Patent: March 17, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar Chhabra, Hemant Kalidas Wadhavankar, Abhijit Anilkumar Jawkar
-
Patent number: 10585999Abstract: Systems and methods for selecting die and package parasitic for an input-output (IO) power domain are described. In one embodiment, the method includes determining a minimum on-die decoupling capacitance based at least in part on a product of a number of simultaneously switching IOs of the die and a maximum instantaneous current of an IO; determining a maximum package inductance based at least in part on a maximum operating frequency of an IC and a target impedance of a power delivery network of the die, the IC package, and a printed circuit board (PCB); and determining a maximum die resistance based at least in part on preventing the maximum die resistance from exceeding a maximum static IR drop of the die.Type: GrantFiled: January 12, 2018Date of Patent: March 10, 2020Assignee: Seagate Technology LLCInventors: Nitin Kumar Chhabra, Rohit Halba
-
Patent number: 10585996Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.Type: GrantFiled: January 12, 2018Date of Patent: March 10, 2020Assignee: Seagate Technology LLCInventor: Nitin Kumar Chhabra
-
Patent number: 10585817Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.Type: GrantFiled: May 29, 2018Date of Patent: March 10, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar Chhabra, Gaurav Mathur, Anant Dalimkar
-
Patent number: 10560116Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.Type: GrantFiled: December 26, 2017Date of Patent: February 11, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
-
Patent number: 10541020Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.Type: GrantFiled: February 27, 2018Date of Patent: January 21, 2020Assignee: SEAGATE TECHNOLOGY LLCInventor: Nitin Kumar Chhabra
-
Publication number: 20190370425Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.Type: ApplicationFiled: May 30, 2018Publication date: December 5, 2019Inventors: Nitin Kumar CHHABRA, Rohit HALBA, Shrikrishna Nana MEHETRE
-
Publication number: 20190370192Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Nitin Kumar CHHABRA, Gaurav MATHUR, Anant DALIMKAR
-
Publication number: 20190267069Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.Type: ApplicationFiled: February 27, 2018Publication date: August 29, 2019Inventor: Nitin Kumar Chhabra
-
Publication number: 20190220560Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: SEAGATE TECHNOLOGY LLCInventor: Nitin Kumar CHHABRA
-
Publication number: 20190220562Abstract: Systems and methods for selecting die and package parasitic for an input-output (IO) power domain are described. In one embodiment, the method includes determining a minimum on-die decoupling capacitance based at least in part on a product of a number of simultaneously switching IOs of the die and a maximum instantaneous current of an IO; determining a maximum package inductance based at least in part on a maximum operating frequency of an IC and a target impedance of a power delivery network of the die, the IC package, and a printed circuit board (PCB); and determining a maximum die resistance based at least in part on preventing the maximum die resistance from exceeding a maximum static IR drop of the die.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: SEAGATE TECHNOLOGY LLCInventors: Nitin Kumar CHHABRA, Rohit HALBA
-
Publication number: 20190199371Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.Type: ApplicationFiled: December 26, 2017Publication date: June 27, 2019Inventors: Nitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
-
Publication number: 20190115912Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.Type: ApplicationFiled: October 17, 2017Publication date: April 18, 2019Inventors: Nitin Kumar Chhabra, Hemant Kalidas Wadhavankar, Abhijit Anilkumar Jawkar
-
Publication number: 20190108301Abstract: A method of generating a chip power model (CPM) for a chip by determining a current profile measurement on a validation board for the chip, and stressing the chip using a plurality of stress factors. A stressed measured waveform is captured and stored. A CPM is generated with the measured waveform captured using the plurality of stress factors. A simulation waveform is captured and stored from the CPM. The measured and simulation waveforms are compared, and when the measured and simulation waveforms do not match, at least one parameter of the CPM is modified iteratively until the measured and simulation waveforms match.Type: ApplicationFiled: October 5, 2017Publication date: April 11, 2019Inventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar, William Harrison Hempy, II, Gaurav Mathur
-
Publication number: 20180373302Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Inventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar