Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.

Abstract: A no load detection and shutdown circuit in an isolated driver is provided. A no load condition is detected by primary side evaluation of a reflected voltage. If a determination is made that a no load condition is present, the no load detection circuit signals a half bridge driver of the driver to cease oscillations, shutting down the driver.

Abstract: A method and apparatus for providing multimodal interaction assistance to customers seeking assistance from agents of an enterprise is disclosed. The method includes augmenting an ongoing voice interaction between a caller and an automated agent with a speech synchronized web session. A session identifier and contextual information in relation to the speech synchronized web session are stored in a database. A display of an option to interact with a human agent is caused during the ongoing speech synchronized web session. In response to a selection of the option by the caller, a co-browsing of the speech synchronized web session by the caller and the human agent is facilitated. The co-browsing of the speech synchronized web session and the contextual information stored in relation to the speech synchronized web session enable the human agent to provide assistance to the caller.

Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.

Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han

Abstract: A computer-method is provided for designing a router network to connect components of an integrated circuit, where the router network comprises a plurality of connected data routing elements. The method comprises generating an undirected graph to represent a mesh of candidate router elements, where the candidate data routing elements are positioned dependent on at least one characteristic of the integrated circuit. The undirected graph comprises a node to represent each candidate data routing element and an edge to represent each connection between the candidate data routing elements.

Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han

Abstract: Provided are embodiments for performing automated defect detection for a flexible member using image processing. The techniques include monitoring, by one or more sensors, a flexible member to obtain sensor data, converting the sensor data from the one or more sensors to image data, and receiving reference image data to compare to the image data. The techniques also include determining a defect based on the comparison and threshold setting information for the flexible member, and transmitting a notification based on the defect.

Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.

Abstract: A device may receive information identifying a development project. The device may determine a set of scripts to assess program code of the development project. The device may execute the set of scripts to perform a project assessment of the development project after determining the set of scripts. The device may generate a user interface including information identifying a result of executing the set of scripts. The result may include information associated with detecting an execution type of error or information associated with detecting a non-execution type of error. The device may communicate with a client device to provide the user interface for display via the client device.

Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.

Abstract: A driver port that provides selectable output currents based on connections thereto, and a driver including the same, is provided. A plurality of shunt resistors are connected in series between a negative output of a driver and a ground. A driver port having a plurality of connection points is provided, each respective connection point connected to a different connection between two of the plurality of shunt resistors. A load including one or more solid state light sources is capable of being connected between one of the connection points of the driver port and a positive output of the driver.

Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.

Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.

Abstract: Systems and methods for selecting die and package parasitic for an input-output (IO) power domain are described. In one embodiment, the method includes determining a minimum on-die decoupling capacitance based at least in part on a product of a number of simultaneously switching IOs of the die and a maximum instantaneous current of an IO; determining a maximum package inductance based at least in part on a maximum operating frequency of an IC and a target impedance of a power delivery network of the die, the IC package, and a printed circuit board (PCB); and determining a maximum die resistance based at least in part on preventing the maximum die resistance from exceeding a maximum static IR drop of the die.

Abstract: The present application provides an improved process for the preparation of sugammadex by reacting a salt of 3-mercapto propionic acid with 6-per-deoxy-6-per-halo-?-cyclodextrin in a suitable organic solvent. This application also provides crystalline form of a salt of 3-mercapto propionic acid, preferably di sodium salt of 3-mercapto propionic acid and its use for the preparation of sugammadex, whereas formula (I) shows the sodium salt of sugammadex.

Abstract: In one example, a method comprises receiving, by a forwarding manager for an internal forwarding path executed by at least one packet processor of a forwarding unit of a network device, one or more packet processing operations from a control unit of the network device; generating, by the forwarding manager based on the one or more packet processing operations, a plurality of nodes each comprising a unique token, wherein a first node of the plurality of nodes includes a token reference set to a value for the token of a second node of the plurality of nodes; configuring, by the forwarding manager based on the nodes, the forwarding path to include respective forwarding path elements for the plurality of nodes; and processing, by the packet processor, a packet received by the forwarding unit by executing the forwarding path elements.

Abstract: In the present disclosure, a request is received from a user to access the electronic device. Upon receiving the request, the user is prompted to perform an action and image frames are captured while the user performs the action. Next, a variation in characteristics of skin of the user is identified, while the user performs the action. The identification is performed using the image frames captured. Upon identification of the variation in the characteristic of the skin of the user, facial features of the user are recognized. The access is provided to the user based on recognition of the facial features.

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

Abstract: Described embodiments provide systems and methods of selecting files to attach to an electronic mail. A server may identify, for each file of a plurality of files, a file context using content of each file. The server may identify, responsive to a request from a client for one or more attachments to add to an electronic mail, a mail context for the electronic mail based at least on content of the electronic mail. The server may compare the file context of at least one of the plurality of files with the mail context of the electronic mail. The server may select one or more files from the plurality of files based on the comparison of the file context with the mail context. The server may provide the client a list of the one or more files for selection as the one or more attachments for the electronic mail.