Patents by Inventor Nitin MAKHIJA

Nitin MAKHIJA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic voltage and frequency scaling (DVFS) within processor clusters
    Patent number: 11797045
    Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 24, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jonathan Masters, Pradeep Kanapathipillai, Manu Gulati, Nitin Makhija
  • Dynamic Voltage and Frequency Scaling (DVFS) within Processor Clusters
    Publication number: 20230093426
    Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.
    Type: Application
    Filed: February 7, 2022
    Publication date: March 23, 2023
    Inventors: Jonathan MASTERS, Pradeep KANAPATHIPILLAI, Manu GULATI, Nitin MAKHIJA