Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

Abstract: Performing thermal management based on temperature evolution models in processor devices is disclosed herein. In some aspects, a processor device provides a cluster thermal management circuit that is configured to determine power consumption measurements for corresponding functional units of a processor core of a plurality of processor cores of a core cluster. The cluster thermal management circuit also determines temperature measurements by corresponding digital thermal sensors (thermal sensor) external to a point of interest (POI) within the processor core. The cluster thermal management circuit generates a predicted temperature at the POI based on a temperature evolution model that correlates power consumption measurements and temperature measurements with the predicted temperature at the POI. If the cluster thermal management circuit determines the predicted temperature at the POI exceeds a thermal mitigation threshold, the cluster thermal management circuit performs a thermal management operation.

Abstract: Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

Abstract: Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

Abstract: Performing dynamic microarchitectural throttling of processor cores based on Quality-of-Service (QOS) levels in processor devices is disclosed herein. In some aspects, a processor device comprises a synchronous core cluster including a plurality of processor cores, a throttling selection circuit, and a throttling circuit. The throttling selection circuit receives a QoS level associated with a workload scheduled for execution by a processor core. The throttling selection circuit determines a performance state of the processor core, and determines a throttling level for the processor core, based on the QoS level and the performance state. The throttling selection circuit provides the throttling level to the throttling circuit, which performs microarchitectural throttling of the processor core based on the throttling level.

Abstract: Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.

Abstract: Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.

Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.