Patents by Inventor Nitin P Gupta
Nitin P Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11036507Abstract: A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.Type: GrantFiled: January 29, 2020Date of Patent: June 15, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Publication number: 20200167159Abstract: A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.Type: ApplicationFiled: January 29, 2020Publication date: May 28, 2020Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Patent number: 10585668Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.Type: GrantFiled: October 2, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Publication number: 20180024833Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.Type: ApplicationFiled: October 2, 2017Publication date: January 25, 2018Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Patent number: 9785439Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.Type: GrantFiled: September 3, 2014Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Publication number: 20150026445Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.Type: ApplicationFiled: September 3, 2014Publication date: January 22, 2015Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Patent number: 8914622Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.Type: GrantFiled: April 30, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Publication number: 20120216023Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.Type: ApplicationFiled: April 30, 2012Publication date: August 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Publication number: 20120102302Abstract: Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.Type: ApplicationFiled: October 20, 2010Publication date: April 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
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Patent number: 7930515Abstract: A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective address is mapped. When a new effective address to physical address mapping needs to be made for a page size, the method accesses the appropriate tables to identify prior mappings for another page size in the same segment. If no such conflicting mapping exists, it creates a new mapping in the appropriate table. A formula is used to generate an index to access a mapping in a table.Type: GrantFiled: July 29, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Nitin P Gupta, Madhavan Srinivasan
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Publication number: 20100030997Abstract: A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective address is mapped. When a new effective address to physical address mapping needs to be made for a page size, the method accesses the appropriate tables to identify prior mappings for another page size in the same segment. If no such conflicting mapping exists, it creates a new mapping in the appropriate table. A formula is used to generate an index to access a mapping in a table.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Applicant: International Business Machines CorporationInventors: Nitin P. Gupta, Madhavan Srinivasan