Patents by Inventor Nitin PARTANI

Nitin PARTANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi supply cell arrays for low power designs
    Patent number: 9483600
    Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Mamta Bansal, Uday Doddannagari, Paras Gupta, Ramaprasath Vilangudipitchai, Parissa Najdesamii, Dorav Kumar, Nitin Partani
  • MULTI SUPPLY CELL ARRAYS FOR LOW POWER DESIGNS
    Publication number: 20150262936
    Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 17, 2015
    Inventors: Mamta BANSAL, Uday DODDANNAGARI, Paras GUPTA, Ramaprasath VILANGUDIPITCHAI, Parissa NAJDESAMII, Dorav KUMAR, Nitin PARTANI