Patents by Inventor Nitin Satishchandra Kabra
Nitin Satishchandra Kabra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11630779Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: GrantFiled: November 17, 2021Date of Patent: April 18, 2023Assignee: Seagate Technology, LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Publication number: 20220075729Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Patent number: 11232037Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.Type: GrantFiled: October 23, 2017Date of Patent: January 25, 2022Assignee: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Sidheshkumar Ramanlal Patel, Sneha Kishor Wagh
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Patent number: 11221956Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: GrantFiled: May 31, 2017Date of Patent: January 11, 2022Assignee: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Patent number: 10921372Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.Type: GrantFiled: July 15, 2019Date of Patent: February 16, 2021Assignee: Seagate Technology LLCInventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
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Publication number: 20190339326Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
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Patent number: 10353001Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.Type: GrantFiled: June 1, 2017Date of Patent: July 16, 2019Assignee: SEAGATE TECHNOLOGY LLCInventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
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Publication number: 20190121740Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.Type: ApplicationFiled: October 23, 2017Publication date: April 25, 2019Inventors: Nitin Satishchandra Kabra, Sidheshkumar Ramanlal Patel, Sneha Kishor Wagh
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Publication number: 20190065404Abstract: Implementations described and claimed herein provide a method and system for adaptive caching in a storage device. The method includes receiving an adaptive caching policy from a host for caching host read data and host write data in a hybrid drive using NAND cache, and allocating read cache for the host read data and write cache for the host write data in the NAND cache based on the adaptive caching policy. In some implementations, the method also includes iteratively performing an input/output (I/O) profiling operation to generate an I/O profile. An adaptive caching policy may be applied based on the I/O profile. When a unit time has completed, a new I/O profile may be compared with a current I/O profile. A new adaptive caching policy is applied based on determining the new I/O profile is different than the current I/O profile.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Nitin Satishchandra Kabra, Rajesh Maruti Bhagwat, Jackson Ellis, Geert Rosseel
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Publication number: 20180349040Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Publication number: 20180348298Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.Type: ApplicationFiled: June 1, 2017Publication date: December 6, 2018Inventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
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Patent number: 10127126Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.Type: GrantFiled: May 13, 2016Date of Patent: November 13, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra
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Publication number: 20170329686Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra
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Patent number: 8850287Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.Type: GrantFiled: October 19, 2012Date of Patent: September 30, 2014Assignee: LSI CorporationInventors: Ramprasad Raghavan, Nitin Satishchandra Kabra, Gurvinder Pal Singh
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Publication number: 20140115418Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: LSI CORPORATIONInventors: Ramprasad Raghavan, Nitin Satishchandra Kabra, Gurvinder Pal Singh
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Patent number: 8099533Abstract: The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).Type: GrantFiled: July 22, 2005Date of Patent: January 17, 2012Assignee: NXP B.V.Inventors: Chee Yu Ng, Nitin Satishchandra Kabra