Patents by Inventor Nitin SRIMAL

Nitin SRIMAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid out of context hierarchical design flow for hierarchical timing convergence of integrated circuits for out of context signoff analysis
    Patent number: 11144694
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nitin Srimal
  • HYBRID OUT OF CONTEXT HIERARCHICAL DESIGN FLOW FOR HIERARCHICAL TIMING CONVERGENCE OF INTEGRATED CIRCUITS FOR OUT OF CONTEXT SIGNOFF ANALYSIS
    Publication number: 20200117845
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventor: Nitin SRIMAL
  • Hybrid out of context hierarchical design flow for hierarchical timing convergence of integrated circuits for out of context signoff analysis
    Patent number: 10552561
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nitin Srimal
  • HYBRID OUT OF CONTEXT HIERARCHICAL DESIGN FLOW FOR HIERARCHICAL TIMING CONVERGENCE OF INTEGRATED CIRCUITS FOR OUT OF CONTEXT SIGNOFF ANALYSIS
    Publication number: 20180068041
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Application
    Filed: October 30, 2017
    Publication date: March 8, 2018
    Inventor: Nitin SRIMAL
  • Hybrid out of context hierarchical design flow for hierarchical timing convergence of integrated circuits for out of context signoff analysis
    Patent number: 9836566
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nitin Srimal
  • HYBRID OUT OF CONTEXT HIERARCHICAL DESIGN FLOW FOR HIERARCHICAL TIMING CONVERGENCE OF INTEGRATED CIRCUITS FOR OUT OF CONTEXT SIGNOFF ANALYSIS
    Publication number: 20170124236
    Abstract: A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 4, 2017
    Inventor: Nitin SRIMAL