Abstract: A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.

Abstract: A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

Abstract: A device and associated method to reduce hold-time violations are disclosed. The device includes a latch module with a selectable delay. The latch module includes a control input to select the delay through the latch. In one embodiment, the delay of the latch is the time between when a latching edge of a clock signal is experienced by the latch until data changes at the output of the latch. In the event of a hold-time violation at latches that are downstream of other latches, a longer delay can be selected at an upstream latch to provide a slower delay path for data provided to the downstream latch violating the hold-time. By providing a slower delay path, the data being latched at the downstream latch will not change as quickly after a latching signal is received, and therefore the possibility of a hold-time violation is reduced.

Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.

Abstract: A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

Abstract: A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.

Abstract: A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.

Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.