Abstract: A charge recycling decoder shares charge between output nodes when input nodes change state.

Abstract: The disclosure describes packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: In general, in one aspect, the disclosure describes a method for use in tracking received out-of-order packets. Such a method can include receiving at least a portion of a packet that includes data identifying an order within a sequence, and based on the data identifying the order, requesting stored data identifying a set of contiguous previously received out-of-order packets having an ordering within the sequence that borders the received packet.

Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.

Abstract: A conditional carry scheduling unit that performs a scheduler carry operation for a round robin scheduler that schedules communication among a plurality of clients who compete to use a shared resource. Each client asserts a request bit to request use of the shared resource, and receives a grant bit from the round robin scheduler that is asserted when the client is scheduled to use the shared resource. The conditional carry scheduling unit includes a plurality of 2-bit carry generation units that operate in parallel. Within each of the 2-bit carry generation units except the initial carry generation unit, two conditional output signals are produced and supplied to a multiplexer tree. The initial carry generation unit assumes a carryin bit of zero, and outputs its carryout bit to the multiplexer tree which determines the actual carries and supplies them back to the carry generation units.