Patents by Inventor Nitish Paliwal

Nitish Paliwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200334179
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • Publication number: 20200328879
    Abstract: An apparatus includes a port with circuitry to implement one or more layers of a Compute Express Link (CXL)-based protocol. The port includes an agent to obtain information to be transmitted to another device over a link based on the CXL-based protocol via a flit, encrypt at least a portion of the information to yield a ciphertext, generate a cyclic redundancy check (CRC) code based on the ciphertext, and cause a flit to be generated comprising the ciphertext. The port is to use the circuitry to transmit the flit and the CRC code to the other device over the link.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Raghunandan Makaram, Ishwar Agarwal, Kirk S. Yap, Nitish Paliwal, David J. Harriman, Ioannis T. Schoinas
  • Patent number: 10614000
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • Publication number: 20200050570
    Abstract: In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Ishwar Agarwal, Nitish Paliwal
  • Publication number: 20200021540
    Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Pratik Marolia, Rajesh Sankaran, Ishwar Agarwal, Nitish Paliwal
  • Publication number: 20190095363
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan