Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

Abstract: Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.

Abstract: Methods, systems, and devices for parallel folding and host write handling are described. A memory system may perform a first program operation on a first die as part of a first folding operation, the first program operation having a duration. During the duration, the memory system may perform at least a portion of a second program operation on a second die as part of a second folding operation and perform a host write. For example, a host system may transmit a command to write data to the memory system during the duration of the first program operation. Based on the command, the memory system may suspend (e.g., delay) the second folding operation to write the data and resume (e.g., initiate) the second program operation after completing the write operation.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: Methods, systems, and devices for adaptive polling for higher density storage are described. A controller of a memory system may identify a temperature of the memory device and select one or more polling parameters that are associated with identifying a status of the memory device based on a temperature of a memory system. In some cases, the controller may perform a polling operation according to the one or more polling parameters based on selecting the one or more polling parameters.

Abstract: Methods, systems, and devices for data separation configurations for memory systems are described. A memory system may store one or more characteristics of data, which may be utilized to improve performance associated with transferring the data between blocks of memory cells. For example, a memory system may be configured to evaluate whether to separate data in one or more transfer operations based on the characteristics of the data. Some transfer configurations may include transferring data independent of characteristics of the data and some other transfer configurations may include transferring data based on characteristics of the data.

Abstract: Methods, systems, and devices for efficient data management for memory system error handling are described. If a new data transfer is desired between the controller and a memory device when the latches are full, the controller may obtain data that has been loaded in one of the latches, temporarily store that data in a buffer, and overwrite the latch with the new data associated with the new data transfer. After the controller is finished working with the new data now stored in the latch, the controller may restore the data from the buffer to the latch so the prior data transfer may continue. This may prevent loss of data or reduce the quantity of data that is temporarily lost from latches and needs to be re-transferred when the latches are full.

Abstract: Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.

Abstract: Methods, systems, and devices for multi-level cell maintenance operations are described. A controller of a memory device may perform a two-portion maintenance operation in order to transfer data from a first block of memory cells to a second block of memory cells. For example, during a first portion of the maintenance operation, the controller may read first data from the first block of memory cells and perform a first error control operation to correct the first data. The controller may store second data associated with the first error control operation to volatile memory of the memory device in response to performing the first error control operation. During a second portion of the maintenance operation, the controller may perform a second error control operation using the second data associated with the first error control operations stored to the volatile memory of the memory device.

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

Abstract: Methods, systems, and devices for determining locations in not-and (NAND) memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence may be received. Information for the boot sequence may be stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells may be selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells may be accessed based on an initialization of the boot sequence.

Abstract: Methods, systems, and devices for techniques for improved data transfer are described. As part of a data transfer operation from a first set of memory cells of a memory device to a second set of memory cells of the memory device, a memory controller of may read a set of data units from the first set of memory cells. The memory device 240 may transmit the set of data units to the memory controller. The memory controller may decode the set of data units, and, in some cases, may generate one or more corrected data units. The memory controller may then generate parity information for the set of data units, and may encode and write the parity information, along with any corrected data units, to the second set of memory cells of the memory device without transferring the uncorrected data units.

Abstract: Methods, systems, and devices for folding operations for improved sequential read performance are described. A memory system may perform a single-die access operation to program data to source data blocks of the memory system. The memory system may reorder the data during folding to destination data blocks of the memory system such that a multi-die access operation may be performed to sequentially read the data from the destination data blocks. For example, data may be programmed to the source data blocks in a first order as part of a single-die access operation, and the data may be folded to the destination data blocks in a second order as part of a single-die access operation, where the supports sequentially reading the data from the destination data blocks as part of a multi-die access operation.

Abstract: Methods, systems, and devices for techniques for concurrent host system access and data folding are described. A memory system may determine to transfer (e.g., fold) data from a set of source data blocks to a set of destination data blocks. The memory system may receive a command to access a first source data block of the set of source data blocks concurrent with the data transfer. The memory system may generate a first order for transferring respective portions of the data that is based on a second order associated with a sequential read of the data from the set of destination data blocks. Based on the accessing the first source data block being concurrent with the data transfer, the first order may exclude a first portion of the data from the first source data block such that the data transfer and the accessing may be concurrently performed.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide media fragmentation management. The controller receives, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file. The controller accesses a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components and determines a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The controller computes a regression level for the file based on the first quantity of read operations relative to a second quantity of LBAs included in the plurality of LBAs.

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

Abstract: Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.