Abstract: A relaying module (68) includes a radio interface (88) and a processor (84). The radio interface is configured to wirelessly receive uplink messages originating in a wireless device (24) that communicates messages with a Base Station (BS) (32) in a communication network (20), and wirelessly transmit repeated uplink messages of at least some of the received uplink messages toward the BS. The processor is configured to hold one or more transmission constraints that define limitations of using network resources for wireless transmissions in the communication network, to receive one or more uplink messages from the wireless device, to select at least some of the received uplink messages for repeated transmission, to allocate to the selected uplink messages respective network resources so as to maximize performance of the communication network under the transmission constraints, and to transmit the selected messages as repeated messages toward the BS, in accordance with the allocated network resources.

Abstract: A relaying module (68) includes a radio interface (88) and a processor (84). The radio interface is configured to wirelessly receive uplink messages originating in a wireless device (24) that communicates messages with a Base Station (BS) (32) in a communication network (20), and wirelessly transmit repeated uplink messages of at least some of the received uplink messages toward the BS. The processor is configured to hold one or more transmission constraints that define limitations of using network resources for wireless transmissions in the communication network, to receive one or more uplink messages from the wireless device, to select at least some of the received uplink messages for repeated transmission, to allocate to the selected uplink messages respective network resources so as to maximize performance of the communication network under the transmission constraints, and to transmit the selected messages as repeated messages toward the BS, in accordance with the allocated network resources.

Abstract: A digital synthesis channelizer includes a memory buffer and circuitry. The memory buffer stores samples of N input signals having a sampling rate Fsi. The N input signals are processed, prior to storing in the memory buffer, by an N-point time-frequency transform module. The circuitry includes at least P filters derived from a Low-Pass Filter whose stopband frequency depends on Fsi. The circuitry is configured to set a sampling time according to a predefined output sampling rate Fso=?·Fsi, ? being a predefined rate-conversion ratio, to select based on the sampling time one or more filters out of the at least P filters, and using the selected one or more filters, to generate, from at least some of the samples in the memory buffer, a filtered and interpolated output sample of an output signal that sums N digitally resampled by ? and frequency-shifted versions of the respective N input signals.

Abstract: A digital synthesis channelizer includes a memory buffer and circuitry. The memory buffer stores samples of N input signals having a sampling rate FSI. The N input signals are processed, prior to storing in the memory buffer, by an N-point time-frequency transform module. The circuitry includes at least P filters derived from a Low-Pass Filter whose stopband frequency depends on Fsi. The circuitry is configured to set a sampling time according to a predefined output sampling rate Fso=?·Fsi, ? being a predefined rate-conversion ratio, to select based on the sampling time one or more filters out of the at least P filters, and using the selected one or more filters, to generate, from at least some of the samples in the memory buffer, a filtered and interpolated output sample of an output signal that sums N digitally resampled by ? and frequency-shifted versions of the respective N input signals.

Abstract: A digital receiver includes a memory buffer and circuitry. The memory buffer stores samples of an input signal having a sampling rate Fsi. The circuitry includes P filter-families that each includes N filters derived from a prototype Low-Pass Filter (LPF) whose stopband frequency depends on an output sampling rate Fso=?·Fsi. The circuitry is configured to set a sampling time according to Fso, to select, based on the sampling time, multiple filter-families out of the P filter-families, and to construct, based on the N filters in each of the selected filter-families, N interpolated filters that are each aligned to the sampling time. The circuitry is further configured to calculate N filtered samples by applying the N interpolated filters to the samples in the memory buffer, and to generate a sample for an output signal of a frequency-slice of the input signal, by digitally down-converting the N filtered samples.