Patents by Inventor Niv Aibester

Niv Aibester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210344782
    Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.
    Type: Application
    Filed: March 11, 2021
    Publication date: November 4, 2021
    Inventors: Yuval Shpigelman, Idan Burstein, Aviv Kfir, Liron Mula, Niv Aibester, Gil Levy
  • Publication number: 20210226895
    Abstract: Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information, Related apparatus and methods are also provided.
    Type: Application
    Filed: January 19, 2020
    Publication date: July 22, 2021
    Inventors: Niv Aibester, Aviv Kfir, Gil Levy, Liron Mula
  • Patent number: 10938720
    Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 2, 2021
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Niv Aibester, Gil Levy, Nir Monovich
  • Publication number: 20200371880
    Abstract: A network element includes multiple ports configured to communicate over a network, a buffer memory, a snapshot memory, and circuitry. The circuitry is configured to forward packets between the ports, to temporarily store information associated with the packets in the buffer memory, to continuously write at least part of the information to the snapshot memory concurrently with storage of the information in the buffer memory, and, in response to at least one predefined diagnostic event, to stop writing of the information to the snapshot memory, so as to create in the snapshot memory a coherent snapshot corresponding to a time of the diagnostic event.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Niv Aibester, Shmuel Shichrur, Barak Gafni
  • Publication number: 20200374230
    Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Niv Aibester, Gil Levy, Nir Monovich
  • Publication number: 20200296057
    Abstract: In one embodiment, a network device includes multiple ports to be connected to a packet data network so as to serve as both ingress and egress ports in receiving and forwarding of data packets including unicast and multicast data packets, a memory coupled to the ports and to contain a combined unicast-multicast user-pool storing the received unicast and multicast data packets, and packet processing logic to compute a combined unicast-multicast user-pool free-space based on counting only once at least some of the multicast packets stored once in the combined unicast-multicast user-pool, compute an occupancy of an egress queue by counting a space used by the data packets of the egress queue in the combined unicast-multicast user-pool, apply an admission policy to a received data packet for entry into the egress queue based on at least the computed occupancy of the egress queue and the computed combined unicast-multicast user-pool free-space.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Liron Mula, Niv Aibester, Barak Gafni
  • Patent number: 10601714
    Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 24, 2020
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
  • Patent number: 10250530
    Abstract: Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 2, 2019
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Niv Aibester, Amir Roitshtein, Barak Gafni, George Elias, Itamar Rabenstein
  • Publication number: 20180241677
    Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.
    Type: Application
    Filed: April 26, 2018
    Publication date: August 23, 2018
    Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
  • Patent number: 10015112
    Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 3, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Amir Roitshtein, Niv Aibester, Barak Gafni, George Elias
  • Patent number: 9985910
    Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 29, 2018
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Eyal Srebro, Sagi Kuks, Niv Aibester
  • Publication number: 20170373989
    Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Eyal Srebro, Sagi Kuks, Niv Aibester
  • Publication number: 20170264571
    Abstract: Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Niv Aibester, Amir Roitshtein, Barak Gafni, George Elias, Itamar Rabenstein
  • Publication number: 20170163567
    Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 8, 2017
    Inventors: Amir Roitshtein, Niv Aibester, Barak Gafni, George Elias