Patents by Inventor Niv Amit

Niv Amit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080127019
    Abstract: Disclosed is a system and method for designing a register layout. According to some embodiments of the present invention, a technology specification is combined with project specifications to produce a set of project specific layout constraints. The project specific constraints may be used to produce a layout.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 29, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Niv Amit, Ofer Geva, Lidor Goren, Alon Margalit, Robert Alan Philhower, Alex Raphayevich, Amir Turi
  • Patent number: 7331029
    Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: February 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Patent number: 7318212
    Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: January 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Patent number: 7290235
    Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Publication number: 20070067749
    Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Applicant: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Publication number: 20070067750
    Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Applicant: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Publication number: 20070067748
    Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Applicant: International Business Machines Corporation
    Inventors: Niv Amit, Ronit Bustin, Lidor Goren, Omer Heymann, Moshe Leibowitz, Gil Noy, Alex Raphayevich, Maya Speiser
  • Publication number: 20040100783
    Abstract: An articulated backplane retainer system for electronic cards containing rigid and flexible domains. A rigid domain may be connected in some embodiments to an appended rigid domain carrying a connector for additional card. Brackets borne by the rigid domain may be used for ruggedizing the card-connector-rigid domain structure. Further ruggedization may be obtained by swivel connection between a rigid domain and an appended rigid domain. To further mechanically secure and limit the flexible backplane of the invention, a chain link member is provided for connecting flexibly pairs of rigid domains.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 27, 2004
    Inventor: Niv Amit