Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: A distributed switchless system characterized by full mesh connectivity is disclosed. The full mesh distributed switchless system allows direct and indirect communication between a source node and a destination node. In direct communication, data propagates via links connecting the source and destination nodes. In indirect communication, data is first sent to an intermediate node via links connecting the source and intermediate nodes. The intermediate node sends the data to the destination node via links connecting the intermediate node and the destination node. The traffic can be divided into all available links across the nodes, rather than only the links connecting the source and destination nodes. Because indirect communication uses more links compared to direct communication, the traffic in each link is smaller. Consequently, the switchless distributed interconnect system can operate with fewer links between any two nodes and links with smaller bandwidth.

Abstract: A passive connectivity optical module (“PassCOM”) is disclosed. A PassCOM is a passive device without a switching functionality. A PassCOM connects links between a plurality of nodes using replaceable plugs. The device can be used for an internal inter-node switching system, where each node is capable of sending data to a destination using a specific link. A source node sends data through a particular link that is connected to a link from a destination node in the PassCOM. Data is first sent from a source node through a link connecting the source node and the PassCOM, then the data is transmitted, through a plug, to the destination node using a link connecting the PassCOM and the destination.

Abstract: A switching Clos network universal element that can dynamically change its role is disclosed. The universal element contains a matrix of VCSELs and a matrix of photodiodes on top of an electro-optical chip. The matrix of VCSELs sends data via a first set of optical links, and the matrix of photodiodes receives data a second set of optical links. The universal element also receives and sends data through electronic links. The universal element can function as an expander, aggregator or transitive switch in a folded Clos network. As an expander or an aggregator, the universal element uses its optical links as ingress links and its electronic links as egress links. Using this universal element, a network can be constructed without separate switching elements. Multiple universal elements can be positioned on a PCB, and the multiple universal elements can function as one switch.

Abstract: A multi-chassis router with passive interconnect and distributed switchless interconnect for connecting a plurality of nodes in full mesh is disclosed. This system allows direct and indirect communication between a source node and a destination node. In direct communication, data propagates via links connecting the source and destination nodes. In indirect communication, data is first sent to an intermediate node via links connecting the source and intermediate nodes. The intermediate node sends the data either to the destination node via links connecting the intermediate node and the destination node. A passive device with replaceable plugs connects the plurality of nodes in full mesh. The passive device facilitates setting up and updating a network.

Abstract: A method of error mitigation for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method including grouping a pre-selected number of high speed interconnect protocol words to form a protection frame, adding at least one additional error protection bit to each word in the group, adding a synchronization bit to each word, using the synchronization bit in a first word in each frame for synchronization of the protection frame and detecting and correcting a single bit error in the protection frame using the additional error protection bits, thereby reducing packet drop when the frames are transferred over the high speed data interconnect.

Abstract: A multi-chassis router with passive interconnect and distributed switchless interconnect for connecting a plurality of nodes in full mesh is disclosed. This system allows direct and indirect communication between a source node and a destination node. In direct communication, data propagates via links connecting the source and destination nodes. In indirect communication, data is first sent to an intermediate node via links connecting the source and intermediate nodes. The intermediate node sends the data either to the destination node via links connecting the intermediate node and the destination node. A passive device with replaceable plugs connects the plurality of nodes in full mesh. The passive device facilitates setting up and updating a network.

Abstract: A passive connectivity optical module (“PassCOM”) is disclosed. A PassCOM is a passive device without a switching functionality. A PassCOM connects links between a plurality of nodes using replaceable plugs. The device can be used for an internal inter-node switching system, where each node is capable of sending data to a destination using a specific link. A source node sends data through a particular link that is connected to a link from a destination node in the PassCOM. Data is first sent from a source node through a link connecting the source node and the PassCOM, then the data is transmitted, through a plug, to the destination node using a link connecting the PassCOM and the destination.

Abstract: A switching Clos network universal element that can dynamically change its role is disclosed. The universal element contains a matrix of VCSELs and a matrix of photodiodes on top of an electro-optical chip. The matrix of VCSELs sends data via a first set of optical links, and the matrix of photodiodes receives data a second set of optical links. The universal element also receives and sends data through electronic links. The universal element can function as an expander, aggregator or transitive switch in a folded Clos network. As an expander or an aggregator, the universal element uses its optical links as ingress links and its electronic links as egress links. Using this universal element, a network can be constructed without separate switching elements. Multiple universal elements can be positioned on a PCB, and the multiple universal elements can function as one switch.

Abstract: A distributed switchless system characterized by full mesh connectivity is disclosed. The full mesh distributed switchless system allows direct and indirect communication between a source node and a destination node. In direct communication, data propagates via links connecting the source and destination nodes. In indirect communication, data is first sent to an intermediate node via links connecting the source and intermediate nodes. The intermediate node sends the data to the destination node via links connecting the intermediate node and the destination node. The traffic can be divided into all available links across the nodes, rather than only the links connecting the source and destination nodes. Because indirect communication uses more links compared to direct communication, the traffic in each link is smaller. Consequently, the switchless distributed interconnect system can operate with fewer links between any two nodes and links with smaller bandwidth.

Abstract: Regular expression matching is performed on a sequence of characters using a pipeline architecture of regular expression matching stages. Multiple regular expression matching stages are connected together in a pipeline manner, with each of these regular expression matching stages corresponding to a different portions of the regular expression. These stages are response to indications from their immediately preceding stages (if they have a preceding stage) of whether or not a progressive match was determined. If all preceding stages matched for corresponding characters of the sequence of characters, then a stage will identify whether or not the current character matches its programmed portion of the regular expression to a next stage or to another device (e.g., the final stage may indicate to a packet processor whether or not the regular expression is matched).

Abstract: Regular expression matching is performed on a sequence of characters using a pipeline architecture of regular expression matching stages. Multiple regular expression matching stages are connected together in a pipeline manner, with each of these regular expression matching stages corresponding to a different portions of the regular expression. These stages are response to indications from their immediately preceding stages (if they have a preceding stage) of whether or not a progressive match was determined. If all preceding stages matched for corresponding characters of the sequence of characters, then a stage will identify whether or not the current character matches its programmed portion of the regular expression to a next stage or to another device (e.g., the final stage may indicate to a packet processor whether or not the regular expression is matched).

Abstract: An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.