Patents by Inventor Nivasan Yogeswaran

Nivasan Yogeswaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240402594
    Abstract: A semiconductor device and method of manufacturing the semiconductor device is disclosed. A layer of metallic material is deposited onto a substrate, the layer having a top surface. At least an edge area of the layer is masked with a first lithography mask and metallic material is removed from the edge area according to the first mask, whereby a first portion of the edge area has a thickness intermediate to the substrate and the layer top surface. The first portion of the edge area is masked with a second lithography mask and metallic material is removed from the first portion according to the second mask, whereby second portions of the edge area are free of deposited metallic material.
    Type: Application
    Filed: May 29, 2024
    Publication date: December 5, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Nivasan Yogeswaran, Ian Cousins, Mark Andrzej Gajda
  • Publication number: 20240332108
    Abstract: A method of manufacturing a semiconductor device, such as a power MOSFET, including: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, the passivation slot is at least partially positioned over the metal layer, and the passivation slot divides the passivation layer into multiple regions, each region experiences a reduced tensile stress ?SiNx as a result of the passivation slot.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Hamza Hanif Patel, Nivasan Yogeswaran, Mark Andrzej Gajda
  • Publication number: 20240332107
    Abstract: A method of manufacturing a semiconductor device, such as a power MOSFET, including: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, the passivation slot is at least partially positioned over the metal layer, and the passivation slot divides the passivation layer into multiple regions, each region experiences a reduced tensile stress ?SiNx as a result of the passivation slot.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Hamza Hanif Patel, Nivasan Yogeswaran, Mark Andrzej Gajda