Patents by Inventor Nivo Rovedo
Nivo Rovedo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8643119Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.Type: GrantFiled: July 30, 2008Date of Patent: February 4, 2014Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTDInventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
-
Patent number: 8482075Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: GrantFiled: May 10, 2012Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert Robison
-
Publication number: 20120217585Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: International Business Machines CorporationInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
-
Patent number: 8232151Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: GrantFiled: June 23, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
-
Publication number: 20110254059Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: ApplicationFiled: June 23, 2011Publication date: October 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
-
Patent number: 8034692Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: GrantFiled: October 20, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
-
Patent number: 8017483Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.Type: GrantFiled: June 29, 2009Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner A. Rausch, Jian Yu
-
Patent number: 7960798Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.Type: GrantFiled: November 13, 2009Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Zhijiong Luo, Ricky S. Amos, Nivo Rovedo, Henry K. Utomo
-
Publication number: 20110089499Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: ApplicationFiled: October 20, 2009Publication date: April 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
-
Publication number: 20100330763Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner A. Rausch, Jian Yu
-
Patent number: 7785950Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.Type: GrantFiled: November 10, 2005Date of Patent: August 31, 2010Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd, Chartered Semiconductor Manufacturing LtdInventors: Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh
-
Publication number: 20100059764Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.Type: ApplicationFiled: November 13, 2009Publication date: March 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijiong Luo, Ricky S. Amos, Nivo Rovedo, Henry K. Utomo
-
Patent number: 7618866Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.Type: GrantFiled: June 9, 2006Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Zhijiong Luo, Ricky S. Amos, Nivo Rovedo, Henry K. Utomo
-
Publication number: 20090057755Abstract: Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP ("INFINEON"), SAMSUNG ELECTRONICS CO., LTD.Inventors: Thomas W. Dyer, Oh-Jung Kwon, Nivo Rovedo, O Sung Kwon, Bong-Seok Suh
-
Patent number: 7473608Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.Type: GrantFiled: August 17, 2007Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Jinghong H. Li, Yaocheng Liu, Zhijiong Luo, Anita Madan, Nivo Rovedo
-
Publication number: 20080283934Abstract: A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance.Type: ApplicationFiled: July 30, 2008Publication date: November 20, 2008Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
-
Patent number: 7442618Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.Type: GrantFiled: July 16, 2005Date of Patent: October 28, 2008Assignees: Chartered Semiconductor Manufacturing, LtdInventors: Yung Fu Chong, Brian Joseph Greene, Siddhartha Panda, Nivo Rovedo
-
Patent number: 7442619Abstract: A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance.Type: GrantFiled: May 18, 2006Date of Patent: October 28, 2008Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
-
Publication number: 20080006818Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.Type: ApplicationFiled: June 9, 2006Publication date: January 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijiong Luo, Ricky S. Amos, Nivo Rovedo, Henry K. Utomo
-
Publication number: 20070293016Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Phung T. Nguyen, William C. Wille, Richard Lindsay, Zhao Lun, Yung Fu Chong, Siddhartha Panda